Computer Systems Organization

Slides:



Advertisements
Similar presentations
The CPU The Central Presentation Unit What is the CPU?
Advertisements

The Fetch – Execute Cycle
Computer Architecture and the Fetch-Execute Cycle
Central Processing Unit
The Microprocessor and its Architecture
Damian BrowneLuis PabonPedro Tovar The operation of a computer in executing a program consists of a sequence of Instruction Cycles, with one machine.
Processor Function Topic 3.
The CPU. Parts of the CPU Control Unit Arithmetic & Logic Unit Registers.
CHAPTER 4 COMPUTER SYSTEM – Von Neumann Model
Chapters 5 - The LC-3 LC-3 Computer Architecture Memory Map
Basic Computer Organization, CPU L1 Prof. Sin-Min Lee Department of Computer Science.
Elements of the Computer (How a processor works)
Dale & Lewis Chapter 5 Computing components. Let’s design a computer Generic CPU with registers −Program counter (PC) – 5 bits (size of addresses) −Instruction.
Overview von Neumann Model Components of a Computer Some Computer Organization Models The Computer Bus An Example Organization: The LC-3.
The Computer Processor
CPU Fetch/Execute Cycle
Fetch Execute Cycle Travis Griffiths. Naming Conventions and Disclaimer Individual registers in a particular CPU will have different names depending on.
Computer Science 210 Computer Organization The Instruction Execution Cycle.
SAP1 (Simple-As-Possible) Computer
Lecture 3. Diff b/w RAM and Registers Registers are used to hold data immediately applicable to the operation at hand Registers are used to hold data.
Introduction to Computer Architecture and System
Computer Science 210 Computer Organization The von Neumann Architecture.
Computer Architecture and the Fetch-Execute Cycle
Computer Architecture and the Fetch-Execute Cycle
The CPU Central Processing Unit. 2 Reminder - how it fits together processor (CPU) memory I/O devices bus.
CPU Design. Introduction – The CPU must perform three main tasks: Communication with memory – Fetching Instructions – Fetching and storing data Interpretation.
Computer Architecture Lecture 09 Fasih ur Rehman.
The von Neumann Model – Chapter 4
Chapter 8: The Very Simple Computer
Model Computer CPU Arithmetic Logic Unit Control Unit Memory Unit
The structure COMPUTER ARCHITECTURE – The elementary educational computer.
Fetch-execute cycle.
Computer Systems - Registers. Starter… Discuss in pairs the definition of the following Control Unit Arithmetic and Logic Unit Registers Internal clock.
September 26, 2001Systems Architecture I1 Systems Architecture I (CS ) Lecture 2: Implementation of a Simplified Computer Jeremy R. Johnson Wednesday,
COMPILERS CLASS 22/7,23/7. Introduction Compiler: A Compiler is a program that can read a program in one language (Source) and translate it into an equivalent.
System Unit Working of CPU. The CPU CPU The CPU CPU stands for central processing unit. it is brain of computer It is most important component of the.
Dale & Lewis Chapter 5 Computing components
Computer Organization and Assembly Languages Yung-Yu Chuang 2005/09/29
Structure and Role of a Processor
Designing a CPU –Reading a programs instruction from memory –Decoding the instruction –Executing the instruction –Transferring Data to/From memory / IO.
Jeremy R. Johnson William M. Mongan
Central Processing Unit Decode Cycle. Central Processing Unit Current Instruction Register (CIR) I1 The fetch cycle has transferred an instruction from.
CPUz 4 n00bz.
Chapter 20 Computer Operations Computer Studies Today Chapter 20.
Lec 4-2 Five operations of the machine cycle Fetch- fetch the next program instruction from memory. (PC+1); instruction to IR Decode- decode the instruction.
3.1.4 Hardware a. describe the function and purpose of the control unit, memory unit and ALU (arithmetic logic unit) as individual parts of a computer;
OCR GCSE Computer Science Teaching and Learning Resources
Chapter 10: Computer systems (1)
Lecture 13 - Introduction to the Central Processing Unit (CPU)
Computer Science 210 Computer Organization
Five Execution Steps Instruction Fetch
Computer Science 210 Computer Organization
System Architecture 1 Chapter 2.
Data Representation – Instructions
The Processor and Machine Language
Computer Science 210 Computer Organization
Computer Science 210 Computer Organization
Instruction and Control II
Topic 6 LC-3.
Systems Architecture I (CS ) Lecture 2: A Simplified Computer
The Little Man Computer
THE FETCH-EXECUTE CYCLE.
GCSE OCR 1 The CPU Computer Science J276 Unit 1
Program Execution.
THE FETCH-EXECUTE CYCLE.
Information Representation: Machine Instructions
Objectives Describe common CPU components and their function: ALU Arithmetic Logic Unit), CU (Control Unit), Cache Explain the function of the CPU as.
Computer Architecture
Presentation transcript:

Computer Systems Organization

Example 1: Describe the sequence of events carried out during the machine cycle when executing the following instructions. Address Contents 500 LDA 1000 501 ADD 1001 502 STO 1002 503 JMP 510 1000 4 1001 6 1003

Instruction #1 LDA 1000 – Load to the accumulator the contents of the memory location 1000.

: : : MM 4 4 6 1000 500 4 501 500 Decode 4 CPU R W IR MAR MDR PC TMP 502 503 MM : LDA 1000 LDA 1000 ADD 1001 STO 1002 JMP 510 : : 1000 1001 1002 1003 4 4 6 R W IR MAR MDR PC TMP ACC 1000 500 LDA 1000 4 Data bus Address bus 501 500 LDA 1000 Decode 4 CPU

Instruction #2 ADD 1001 – add the contents of location 1001 and the contents of the accumulator and store the result back in the accumulator.

: : : MM 4 6 6 1001 501 6 501 502 Decode 4 6 CPU 10 R W IR MAR MDR PC 500 501 502 503 MM : LDA 1000 ADD 1001 ADD 1001 STO 1002 JMP 510 : : 1000 1001 1002 1003 4 6 6 R W IR MAR MDR PC TMP ACC 1001 501 6 ADD 1001 Data bus Address bus 501 502 ADD 1001 Decode 4 6 Add CPU 10

Instruction #3 STO 1002 – store the contents of the accumulator to the memory location 1002.

: : : MM 4 6 10 1002 502 10 502 503 Decode 10 CPU R W IR MAR MDR PC 500 501 502 503 MM : LDA 1000 ADD 1001 STO 1002 STO 1002 JMP 510 : : 1000 1001 1002 1002 1003 4 6 10 R W IR MAR MDR PC TMP ACC 1002 502 STO 1002 10 Data bus Address bus 502 503 STO 1002 Decode 10 CPU

Instruction #4 JMP 510 – Jump to memory location 510

: : : MM 4 6 10 503 510 504 503 Decode CPU R W IR MAR MDR PC TMP ACC 500 501 502 503 MM : LDA 1000 ADD 1001 STO 1002 JMP 510 JMP 510 : : 1000 1001 1002 1003 4 6 10 R W IR MAR MDR PC TMP ACC 503 JMP 510 Data bus Address bus 510 504 503 JMP 510 Decode CPU