Chapter 7 High-Speed Signal Prof. Lei He Electrical Engineering Department University of California, Los Angeles URL: eda.ee.ucla.edu

High-speed Links are Everywhere Backbone Router Rack PC or Console [Sredojevic:ICCAD’08]

High-Speed Links: Applications Chip-to-chip signaling n Computers, games: SDRAM(DDR, DDR2) MHZ, RDRAM MHz, DDR MHz, DDR GHz, XDR DRAM GHz Board-to-board n Computers: Peripherals- PCI ( MHz), PCIe (250M- 500M-1GHz), Infiniband (2.5Gb/s) Networks n LAN: Fast Ethernet, Gigabit Ethernet, 10G Ethernet n WAN: OC-12 (625MHz), OC-192(12.5GHz) n Routers: 625Mb/s – 2.5Gb/s

Outline Link Design Basics n Signal Integrity n High Speed Signaling Architectures n Equalization n Post-Silicon Tuning of High-Speed Signaling

Noise Signals may be corrupted from many sources n Inter-symbol interference (ISI) – Frequency-dependent attenuation (dispersion) – Reflection – Oscillation n Crosstalk n Power supply noise n Real noise – Thermal and shot noise n Parameter variation Noise measure n Eye diagram – Timing jitter – Amplitude noise

Inter-Symbol Interference A signal interfering with itself Ideally a transmission system is time invariant n No history of previous bits In reality, the state of the system is affected by previous bits n Signals that don’t reach the rails by the end of cycle – Signal’s transition time is limited by channel bandwidth n Reflections on the transmission lines n Magnitude and phase of excited resonances

ISI - Dispersion Frequency-dependent attenuation In general, channel is low pass n Our nice short pulse gets spread out n Example: a 101 pattern

ISI - Reflection Reflections of previous bits travel up and down transmission lines A mismatch of δ gives (to the first order) a reflection of ρ

ISI - Resonances Oscillations are excited by signal transitions and may interfere with later transitions Excitation of resonant circuits is reduced with longer transition times n Slower edge has less high frequency spectral content Resistance damps oscillation

Crosstalk is the coupling of energy from one line to another via: Mutual capacitance (electric field) Mutual inductance (magnetic field) One signal interfering with another signal Zs Zo Mutual Capacitance, C m Mutual Inductance, L m Zs Zo CmCm LmLm near far near far Crosstalk

The mutual inductance will induce current on the victim line opposite of the driving current (Lenz’s Law) The mutual capacitance will pass current through the mutual capacitance that flows in both directions on the victim line Crosstalk Induced Noise Zs Zo Zs Zo I Cm LmLm near far near far I Lm

Near end crosstalk is always positive Currents from Lm and Cm always add and flow into the node For PCB’s, the far end crosstalk is “usually” negative Current due to Lm larger than current due to Cm Note that far and crosstalk can be positive Driven Line Un-driven Line “victim” Driver Zs Zo Near End Far End Voltage Profile of Coupled Noise

Power Supply Noise The power supply network has parasitic elements n On-chip: resistive n Off-chip: inductive Current draw across these elements induces a noise voltage: Instantaneous current is what matters n May be many times the DC current – 10W chip draws 4A at 2.5V – Peak current may be 10-20A

Simultaneous Switching Outputs (SSO) When several outputs switch simultaneously, significant current is drawn from the supply or sent into ground n Supply connections have inductance n SSO currents produce a voltage drop across these inductances On-chip, the VDD to VSS voltage difference decreases n Effect grows with number of drivers switching n Quadratic with the inverse of transition time Between chips, the drops across VSS inductances can effect driver timing and shift the receiver threshold

Other Noise Sources Alpha particles n 5MeV particle injects 730fC of charge into substrate n One node typically collects less than 50fC Thermal and shot noise n Proportional to bandwidth – typically in the uV Parameter mismatch n V T and β have deviation proportional to 1/sqrt(WL) n Systematic variations depend on layout

Eye Diagram This is a “1” This is a “0” Eye – space between 1 and 0 With timing noise With voltage noise With both!!

Eye Diagram (cont’d) Standard measure for signaling n Synchronized superposition of all possible realizations of the signal viewed within a particular interval Timing jitter n Deviation of the zero-crossing from its ideal occurrence time Amplitude noise n Set by signal-to-noise ratio (SNR) n The amount of noise at the sampling time

Outline Link Design Basics n Signal Integrity n High Speed Signaling Architectures n Equalization n Post-Silicon Tuning of High-Speed Signaling

Signaling – Main Idea A good signaling system isolates the signal from noise rather than trying to overpower the noise n Crosstalk – Terminate both ends, use homogeneous media n ISI – Matched terminations, no resonators, rise-time control n Power supply noise – Avoid coupling into signal or reference  Differential signaling  Current mode  stable reference

Architecture of Signaling

Signaling Architecture Tradeoffs Signal modulation n PAM (Pulse-amplitude modulation) n Pulsed (Return-to-Zero, RZ) signaling n Binary (ex:NRZ) or Multiple-level signaling (MLS) Uni-directional or Bidirectional n Time-multiplexed bidirectional or simultaneous bidir. Single-ended or differential Current mode or voltage mode Bus or single-trace Point-to-point or multi-drop

Example System - Trade-offs

Voltage Mode vs Current Mode Main differences are n Ease of control and generation – Much easier to generate a small current than a small voltage n Coupling of supply noise – 50% of supply noise shows up on the data line in the matched voltage mode; potentially much less in a high-Z current-mode driver n Generation of high-Z switches easier than controlled-Z switches

Single-ended vs Differential Single-ended signaling n compare to shared reference n Often used with a bus n Issues – Generates SSO noise – How to make reference – How to quiet reference – Crosstalk cannot be made common-mode Differential signaling compare between two lines Noise immunity Many noise sources become common mode Issues Differential must run > 2x as fast as single- ended to make sense Otherwise, powerx2, pinsx2

Binary vs Multiple-level (4-PAM) Binary (NRZ) is 2-PAM Use 2-levels to send one-bit per symbol 4-PAM uses 4-levels to send 2 bits per symbol Each level has 2 bit value

When Does 4-PAM Make Sense?

Simultaneous Bidirectional Signaling Wires can transmit waves in both directions It seems a shame to only use one direction at a time Simultaneous Bidirectional Signaling n Transmit waves in both directions at the same time n Waveform on wire is superposition of forward and reverse traveling wave n Subtract transmitted wave at each end to recover received wave There are 3-levels on the line but it’s still 2-level signaling Much more sensitive to reflections and crosstalk

Outline Link Design Basics n Signal Integrity n High Speed Signaling Architectures n Equalization n Post-Silicon Tuning of High-Speed Signaling

Equalization Channel is band-limited, most of them are low-pass Goal is to flatten the overall response Equalization: Boost higher frequencies relative to lower frequencies Can be done at T x or R X or both channel equalizer

Receiver Linear Equalizer Amplifies high-frequencies attenuated by the channel Pre-decision Digital or Analog FIR filter Issues n Also amplifies noise! n Precision n Tuning delays (if analog) n Setting coefficients (adaptive filter) – Adaptive algorithms such as LMS

Transmitter Linear Equalizer Tx Pre-emphasis Filter Attenuates low-frequencies n Need to be careful about output amplitude - limited output power – If you could make bigger swings, you would – EQ really attenuates low-frequencies to match high frequencies n Also FIR filter: D/A converter Can get better precision than R X Issues n How to set EQ weights? n Doesn’t help loss at high f

Tx Linear EQ: Single Bit Response

Outline Link Design Basics n Signal Integrity n High Speed Signaling Architectures n Equalization n Post-Silicon Tuning of High-Speed Signaling

Process Variation vs Analog Circuits [ITRS] Threshold voltage variation is increasingly dominant and is primarily random n Due to increasing and random doping fluctuation Corner-based design is not effective for match used widely in analog circuits n Often results in over-sized circuits and excessive area/power

Post-Silicon Tuning is Effective Post-silicon tuning is effective to compensate random process variation Digitally tunable circuit is commonly adopted n Insensitivity to noise and variation n Suitable for process migration [Li:ICCAD’08]

Post-Silicon Tuning of High-Speed Signaling Algorithm Framework n Problem formulation n Branch and bound based algorithm Case Study I: Transmitter Case Study II: PLL Conclusions

Unit Cell Based Design Methodology Pre-characterize different types of unit cell, e.g., transistor with a given threshold voltage and unit W/L. n A transistor of larger W/L can be synthesized by connecting those unit cells of same type in parallel n Design variables simply become – type of unit cell α(threshold) – number of unit cells in parallel (sizing) n Constraints such as output swing is satisfied for correct operation Apply to other circuit elements such as unit capacitance and resistance Make design better and modeling more accurate

Digitally Tunable Circuits one tap in a pre-emphasis filter current source can be implemented by current-division DAC Current-division DAC is commonly used to combat process variation Two tuning parameters n LSB size ( ): minimum step during digital-to-analog conversion n Resolution ( β ): number of bits used

Impact of Post-Silicon Tuning (a) Without Tuning(b) With Tuning Example: BER for a high-speed link n 4-tap pre-emphasis filter in a transmitter n 0% (3σ) variation in V t Design-time optimization and post-silicon tuning circuit both need area, and joint optimization is must

Joint Optimization parametric yield power constraint. Process variation changes power area constraint. Process variation does not change layout area bound on design parameters bound on the total number of unit cells types bound on the LBS and resolution e

Optimization Challenges Discrete problem with non-convex objective and constraints Solution space surface is rough and many local maxima exist Significant improvement can be expected 3000 Monte Carlo runs over different unit cell design α, resolution β, and LSB size for one tap of FIR

Algorithm framework :  Partition the solution space by LSB size ( ) and unit cell type (α)  Develop a bound on the parametric yield  Discard (fathom) if bound worse than the current best solution Overall Algorithm n Use gradient ascent method to find the local maxima – Sequentially take steps in the direction proportional to the gradient. Bound estimation n Remove the area and power constraints n Use LMS algorithm to find optimal yield value

Gradient Ascend Method In each un-pruned region, sequentially take steps in direction proportional to the gradient, until a local maximum of the objective function is reached. At each step, increase/decrease each variable by 1 in turn and check the change of the objective function. Always take the change (direction) that causes the maximum increase. Termination of the algorithm indicates that one of the local maxima has been reached or that we have reached the boundary. The initial guess for the GDA can be arbitrarily chosen. In our experiments, we find that it did not influence runtime or quality significantly. We also observed that the algorithm always converges to local optimum within two or three iterations.

Post-Silicon Tuning of High-Speed Signaling Algorithm Framework Case study 1: transmitter n Knobs for design-time and post-silicon n Modeling and formulation n Experimental results Case Study 2: PLL Conclusions

Knobs for Optimization Given transmission channel → filter coefficient → transistor size change channel behavior ← parasitic capacitance

Knobs for Optimization

Problem Formulation For transmitter n, random variable

BER Distribution Comparison n 20% (3σ) variation in V th with Monte Carlo runs n Design 1 - without tuning circuit – All resources are used for filter – Unavoidable large variation n Design 2 - one tap filter – All resources are used for DAC – Has extreme small variance but suffers severe ISI n Design 3 – heuristic design – Assume 4-tap filter – Assume LSB size is equal for each tap – Limit the solution space – Good improvement compared to two extreme cases n Design 4 - our algorithm – Provides better solution (mean, variance)

Yield Rate Experiment setting n Channel – 30cm differential microstrip line with FR-4 substrate n 5GHz data rate n Yield is set by BER=1e-15 (estimated by EVM) Yield comparison for different area constraints area  Our algorithm always provide better yield than design heuristic  With aggressive area constraint, our algorithm has much less yield degradation  Saturation effect  Up to 47% improvement

Yield with Power Constraint v t variationpower

Post-Silicon Tuning of High-Speed Signaling Algorithm Framework Case study 1: Transmitter Case study 2: PLL Design Conclusions

PLL output clock jitter H nin and H nVCO are the noise transfer function of reference clock noise and VCO noise n E.g. Jitter Modeling [Mansuri:JSSC’02] Tunable PLL  Jitter can be changed by tuning the charge pump current ratio

Joint Optimization Design-time optimization n Two charge pumps I cp1, I cp2 n Ratio (I cp1 / I cp2 ) determines output RMS jitter n Optimal ratio can be found using design-time optimization Again, process variation would cause performance degradation Digitally tuned current mirror n Small reference current – Consumes less power – η need to be far less than unity – Limited tuning resolution n Large reference current – Good tunability – Power and area penalty [Horowitz:JSSC’00]

Same Formulation Applies For PLL objective function becomes and area can be computed in a way similar to the transmitter case.

Experimental Results PLL with digitally controlled charge pump current Yield is defined by output clock RMS jitter Design heuristic using minimized biasing current Consider 30% V th variation Improve the yield by up to 56%

Conclusions Formulate a joint optimization problem for digitally tuned analog circuits n Consider both design-time optimization and post-silicon tuning n Maximize performance yield s.t. power and area constraints Propose a general optimization framework n Combine branch-and-bound and gradient-ascent algorithm n Effectively find the global optimum Two joint optimization design examples for high-speed serial link n Transmitter design n PLL design Experiments show great (>47%) yield improvement over common circuit design heuristic