Author George Peck EVLA Hardware Monitor & Control PDR March 13, 2002 1 MIB FUNCTIONALITY.

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Presentation transcript:

Author George Peck EVLA Hardware Monitor & Control PDR March 13, MIB FUNCTIONALITY

Author George Peck EVLA Hardware Monitor & Control PDR March 13, INTERFACE TO ETHERNET Ethernet Protocol Drives the Probable Need For RTOS Kernel In MIB Ethernet Protocols to be Used – Probably TCP/IP, UDP, ICMP Multiple Commands or Monitors Can be Sent in a Single Ethernet Frame

Author George Peck EVLA Hardware Monitor & Control PDR March 13, RTOS Will Implement TCP/IP Stack May Also be Used to Prioritize Tasks and Handle Interrupts Should be as Compact as Possible We Want to Obtain the RTOS Source Code

Author George Peck EVLA Hardware Monitor & Control PDR March 13, COMMANDS Commands Can be Queued for Implementation at an Absolute Time Commands Can be Sent for Immediate Implementation Commands Are Addressed to an Individual MIB A Single Command Can Cause the MIB to Implement Multiple Actions

Author George Peck EVLA Hardware Monitor & Control PDR March 13, MONITOR DATA VALUES MIB Can Periodically Send Monitor Data Values Monitor Data Values Can be Requested by Control Computer All Monitor Data Values are Time Stamped Monitors Are Addressed to a Specific Destination Target

Author George Peck EVLA Hardware Monitor & Control PDR March 13, MIB TO MIB COMMUNIUCATION Some MIB to MIB Communication Would Be Beneficial, and is Planned

Author George Peck EVLA Hardware Monitor & Control PDR March 13, LOADING OF CODE MIB Loads Code From Flash Memory on MIB and Module at Power Up MIB Firmware Runs From On-Chip Memory Flash Memory on Module Can be Loaded by Ethernet

Author George Peck EVLA Hardware Monitor & Control PDR March 13, MODULE SERIAL NUMBER, SLOT ID MIB Will Obtain Module Serial Number and Slot ID From the Module

Author George Peck EVLA Hardware Monitor & Control PDR March 13, SAFETY OF MODULE The MIB will NOT Implement Tasks Necessary for Safety or Protection of Module

Author George Peck EVLA Hardware Monitor & Control PDR March 13, A/D AND D/A CAPABILITIES A/D And D/A Capabilities Will NOT be Directly Implemented by the MIB The MIB Will Communicate With A/D and D/A Converters on the Module Via SPI

Author George Peck EVLA Hardware Monitor & Control PDR March 13, TIMING PULSES AVAILABLE TO MIB 1 PPS 10 Second Pulse 19.2 Hz (Transition) 10 ms

Author George Peck EVLA Hardware Monitor & Control PDR March 13, TIME On Board Timer Will Keep Absolute Time to At Least 10 ms Resolution Time Will be Obtained From Control Computer Ahead of a Timing Pulse, and the Timer Will Start at the Arrival of the Pulse