Dataflow Modeling of Signal Processing and Communication Systems Wireless Networking and Communications Group 8 December 2015 Prof. Brian L. Evans Guest Lecture for EE 382V Embedded System Design and Modeling

2 Outline  Introduction  Signal processing system design needs  Synchronous dataflow  Signal processing building blocks  Filters  Rate changers  Signal processing examples  Communication system examples  Conclusion 2

3 Needs for System-Level Design  Signal processing algorithms  Multirate processing: e.g. interpolation  Local feedback: e.g. IIR filters  Iteration: e.g. decoding  Graphical representations  Block diagram syntax natural but static  Dataflow semantics for signal processing  Signal representations  Bit, byte, integer, fixed-point, floating-point  Complex-valued versions of above  Vectors/matrices of scalar data types Do not need recursion Often iterative Bit error rate vs. Signal- to-noise ratio (Eb/No)

4 4 Needs for Embedded Realization  Block-based and point-by-point processing  Retarget simulation for embedded platforms  Processors (e.g. DSPs) and hardware (e.g. FPGAs)  Cosimulation on desktop and embedded platforms  Static scheduling  Prediction of resources (e.g. memory) at compile time  DSPs have limited on-chip memory ( kB)  FPGAs have limited on-board memory & logic blocks  Floating-point to fixed-point conversion

5 5 Dataflow Models  Match data-intensive processing  Signal processing  Communication systems  Definitions [Lee]  A token is a data value or data structure  A signal is a sequence of tokens  A node maps input tokens onto output tokens  Set of firing rules specify when a node can fire  A firing of a node consumes input tokens and produces output tokens  A sequence of firings is a dataflow process

6 6 Synchronous Dataflow [Lee 1987]  Untimed  Arcs: one-way first-in first-out (FIFO) queues  Nodes: functional blocks Source nodes always enabled Others enabled when enough samples are on all inputs  Node execution Consumes same fixed number of samples on each input arc Produces same fixed number of tokens on each output arc Consumed data is dequeued from arc  Flow of data through graph does not depend on data values A 3 B 2

7 7 Synchronous Dataflow (SDF)  Delay of (n) samples n samples initially in FIFO queue  Systems are determinate Execution in sequence or parallel has same outcome (predictable)  Systems can be statically analyzed Check for “sampling rate” consistency Determine/optimize FIFO queue sizes at compile time  Models systems with rational rate changes A 3 B 2 (6)2 3 Nodes are not multirate but graph is! Periodic schedule fires A twice & B thrice, e.g. AABBB or ABABB

8 8 Dataflow Models in Design Tools Design ToolDataflow Model(s)Example Applications Agilent Advanced Design System Synchronous and Timed Synchronous Dataflow Mixed analog, digital, and RF communication systems Coware Signal Proc. Worksystem Synchronous and Dynamic Dataflow Periodic digital systems, e.g. transceivers & MP3 decoders National Instruments LabVIEW Homogeneous Dynamic Dataflow (G) Periodic and aperiodic digital systems Synopsys CoCentric System Design Studio Cyclostatic DataflowPeriodic digital systems, e.g. transceivers & mp3 decoders UC Berkeley Ptolemy Classic Synchronous and Dynamic Dataflow Periodic and aperiodic digital systems

9 Outline  Introduction  Signal processing system design needs  Synchronous dataflow  Signal processing building blocks  Filters  Rate changers  Signal processing examples  Communication system examples  Conclusion 9

10 Homogeneous Operations  Pointwise arithmetic operations (addition, etc.)  Delay by m samples property of SDF arc  Finite impulse response filter op 11 1  … … 1 1 FIR

11 Homogeneous Operations  Infinite impulse response filter  x[k]x[k] y[k]y[k] y[k-M]y[k-M] x[k-1] x[k-2] b2b2 b1b1 b0b0 Unit Delay x[k-N]x[k-N] bNbN Feed- forward a1a1 a2a2 y[k-1] y[k-2] Unit Delay aMaM Feedback IIR

12 12 Increasing Sampling Rate  Upsampling by L denoted as L Outputs input sample followed by L-1 zeros Increases sampling rate by factor of L  Finite impulse response (FIR) filter g[m] Fills in zero values generated by upsampler Multiplies by zero most of time (L-1 out of every L times)  Sometimes combined into rate changing FIR block m Output of Upsampler by Output of FIR Filter m 012 Input to Upsampler by 4 n 0 g[m]g[m] FIR 1 4

13 13 Polyphase Filter Bank Form  Filter bank (right) avoids multiplication by zero Split filter g[m] into L shorter polyphase filters operating at lower rate (no loss in output precision) Saves factor of L in multiplications and prev. inputs stored and increases parallelism by factor of L g0[n]g0[n] g1[n]g1[n] g L-1 [n] s(Ln) s(Ln+1) s(Ln+(L-1)) g[m]g[m] L Oversampling filter a.k.a. Pulse shaper a.k.a. Linear interpolator Multiplies by zero (L-1)/L of the time 1 L L 1

14 Decreasing Sampling Rate  Finite impulse response (FIR) filter g[m] Typically a lowpass filter Enforces sampling theorem  Downsampling by L denoted as L Inputs L samples Outputs first sample and discards L-1 samples Decreases sampling rate by factor of L  Sometimes combined into rate changing FIR block g[m]g[m] Input to Downsampler m 0 12 Output of Downsampler n 0 FIR 4 1

15 15 Polyphase Filter Bank Form  Filter bank (right) only computes values output Split filter h[m] into M shorter polyphase filters operating at lower rate (no loss in output precision) Saves factor of M in multiplications and increases parallelism by factor of L h0[n]h0[n] h1[n]h1[n] h M-1 [n] h[m]h[m] M s(Mn) s(Mn+1) s(Mn+(M-1)) Undersampling filter a.k.a. Matched filter + sampling a.k.a. Linear decimator Outputs discarded (M-1)/M of the time 1 1 MM

16 Outline  Introduction  Signal processing system design needs  Synchronous dataflow  Signal processing building blocks  Filters  Rate changers  Signal processing examples  Communication system examples  Conclusion 16

17 17 Spectral Shaping for Converter  Upsampling by 4 Output input sample then 3 zeros Increases sampling rate fourfold  FIR filter performs interpolation kHz [Pohlmann] Digital 4x Oversampling Filter 4 FIR Filter f stop < kHz 16 bits kHz Spectral shaping for an audio data converter

18 Noise-Shaped Feedback Coding  Homogeneous. Computable? b(m)b(m) + _ _ + e(m)e(m) x(m)x(m) differencequantizer compute error (noise) shape error (noise) u(m)u(m) Sigma-delta modulator using noise-shaped feedback coding (spectral shaping) Original ImageThreshold at Mid-Gray Noise-Shaped

19 Outline  Introduction  Signal processing system design needs  Synchronous dataflow  Signal processing building blocks  Filters  Rate changers  Signal processing examples  Communication system examples  Conclusion 19

20 20 Communication Systems  Message signal m[k] is information to be sent Information may be voice, music, images, video, data Low frequency (baseband) signal centered at DC  Transmitter signal processing includes lowpass filtering to enforce transmission band  Transmitter carrier circuits upconvert signal Signal Processing Carrier Circuits Transmission Medium Carrier Circuits Signal Processing TRANSMITTERRECEIVER s(t)s(t) r(t)r(t) CHANNEL

21 21 Communication Systems  Propagating signals experience attenuation & spreading w/ distance  Receiver carrier circuits downconvert to an intermediate frequency and possibly baseband  Receiver signal processing extracts/enhances baseband signal Signal Processing Carrier Circuits Transmission Medium Carrier Circuits Signal Processing TRANSMITTERRECEIVER s(t)s(t) r(t)r(t) CHANNEL Model the environment

22 22 Quadrature Amplitude Modulation i[n]i[n] gT[m]gT[m] L + cos(  0 m) q[n]q[n] gT[m]gT[m] L sin(  0 m ) Serial/ parallel converter 1 Bits Map to 2-D constellation J L samples per symbol (upsampling) Digital QAM Transmission Pulse shaper (FIR filter) Index Signal Processing Carrier Circuits Transmission Medium Carrier Circuits Signal Processing TRANSMITTERRECEIVER s(t)s(t) r(t)r(t) CHANNEL

23 23 Quad. Amplitude Demodulation i est [n] h opt [m] L cos(  0 m) h opt [m] L sin(  0 m ) L samples per symbol (downsampling) Matched filter (FIR filter) q est [n] Parallel/ serial converter J Bits Decision Device 1 Digital QAM Reception Symbol Signal Processing Carrier Circuits Transmission Medium Carrier Circuits Signal Processing TRANSMITTERRECEIVER s(t)s(t) r(t)r(t) CHANNEL h eq [m] Channel equalizer (FIR filter)

24 Modeling of Points In-Between  Baseband channel model  Combines transmitter carrier circuits, channel and receiver carrier circuits  One model uses cascade of gain, FIR filter, and additive noise (homogeneous SDF) Signal Processing Carrier Circuits Transmission Medium Carrier Circuits Signal Processing TRANSMITTERRECEIVER s(t)s(t) r(t)r(t) CHANNEL FIR + noise

25 Limitations of SDF  Strengths of SDF are also its limitations  Untimed  Predictable flow of data through graph  Modeling of receiver front end  Automatic gain control (AGC)  Symbol clock recovery (digital IIR)  Receive filter (analog IIR) 25 Receive Filter A/D Symbol Clock Recovery Carrier Detect AGC Analog front end for QAM reception

26 26 Conclusion  Synchronous dataflow model does not support  Composability with itself  Data-dependent graphs  Recursion  Advantages  Models multirate systems  Ability to generate static schedules at compile time (resources required by graph known in advance)  Static sequential schedules can be optimized for minimum program memory or buffer memory  SDF modeling allows efficient simulation and synthesis  SDF well-matched to signal processing and communications Synchronous dataflow is untimed and determinate Limited expressiveness enables SDF to be statically scheduled

27 27 Thank You, Questions ?