E X C E E D I N G E X P E C T A T I O N S VLIW-RISC CSIS Parallel Architectures and Algorithms Dr. Hoganson Kennesaw State University Instruction Sets Instruction Set: the set of instructions that the CPU has been designed to perform Defines the Machine Code, and Assembly Language One major area of variation is the handling of OPERANDS OPERANDS - the data values that the instruction works with –Register operands - values store in the CPU in registers –Memory operands - values stored in memory, that must be loaded into the CPU before the instruction can be executed Instruction sets vary –as to how many operands from memory are allowed –how many total instructions in the set –can an instruction be fetched and used in same instruction?

E X C E E D I N G E X P E C T A T I O N S VLIW-RISC CSIS Parallel Architectures and Algorithms Dr. Hoganson Kennesaw State University CISC CISC - Complex Instruction Set Computer Large set of instruction Instructions are complex: they can do many things and operate upon multiple operands Can execute instructions that also require operands from memory Increases cost/size/transistor count of the instruction decoder STRUCTURAL HAZARDs present with pipelines –Instruction Fetch and Operand Fetch

E X C E E D I N G E X P E C T A T I O N S VLIW-RISC CSIS Parallel Architectures and Algorithms Dr. Hoganson Kennesaw State University RISC RISC - Reduced Instruction Set Computer Instructions that fetch or store operands do nothing else Fewer instructions in set reduces STRUCTURAL HAZARDS - allowing higher speedups with more pipelines and more stages per pipeline more instructions required to do the same work DESIGN TRADEOFF - RISC is less work per instruction, but supports more instructions per time unit with high pipeline speedups

E X C E E D I N G E X P E C T A T I O N S VLIW-RISC CSIS Parallel Architectures and Algorithms Dr. Hoganson Kennesaw State University RISC/CISC Sim Lab Demo of simulator CISC architecture - –Single pipe –five stages –1000 instructions, –single processor –flush and stall at 0.0 –100 interations –=3.982 Speedup CISC with flush at 30%-70% ( ) –= 1.35

E X C E E D I N G E X P E C T A T I O N S VLIW-RISC CSIS Parallel Architectures and Algorithms Dr. Hoganson Kennesaw State University RISC/CISC Sim Lab RISC architecture - –Single pipe –five stages –2000 instructions, –single processor –flush at –100 interations –=3.35 Speedup

E X C E E D I N G E X P E C T A T I O N S VLIW-RISC CSIS Parallel Architectures and Algorithms Dr. Hoganson Kennesaw State University Simulation comparison CISC at 1.35 speedup for 1000 instructions = 1/1.35 time units –0.74 time RISC at 3.35 speedup for 2000 instructions = 2/3.35 time units –0.59 time Even though the RISC machine had to do twice as many instructions for the same amount of work, because it ran at higher speedups, it completed the workload in less time.

E X C E E D I N G E X P E C T A T I O N S VLIW-RISC CSIS Parallel Architectures and Algorithms Dr. Hoganson Kennesaw State University VLIW VLIW - Very Long Instruction Word Convert CISC instructions to RISC instructions Store converted instructions in VLIW Send VLIW to RISC execution core for execution on multiple pipelines