Data Management for Decision Support Session-4 Prof. Bharat Bhasker

Client Server Computing Cooperative processing- Request Response Model RPC Vs. Protocols Client Server architecture can be based on software only, meaning the Client and Server components can be residing and sharing the same processors. Client Server Client

Client Server Computing Three Tier Architecture Client Data Servers Server Unix Server Netware Server Win/NT Application Servers Client

Server Requirements Multi-user/ Concurrent Access Scalability- Given increase in the size of problem, no of users etc. can be handled by increasing proportionate resources without deterioration in performance. If problem P is solved by current resources in time T. If problem size is N*P and resources are augmented to N times the time taken is T1. Scalability is T/T1. ( Ideally 1) Speedup- Problem P in T. Increase resources to M times, Time taken is T1. Speed up is T/T1 (Ideal value M) Capacity Availability MM, Networking and Communications

Server Hardware Architecture Cycle Time- is inverse of system’s clock rate, depends on underlying chip technology. PC’s MHz. Faster the clock rate denser the chip technology. Path Length- number of m/c instructions required to execute one command. Shorter the path length, higher the resulting performance. Depends upon the underlying instruction set and optimizing compilers. Cycles/instruction (cpi) - how many clock cycles are needed to execute one instruction. Some machines may execute more than one instruction in a cycle ( 1). CPI is 1 is Risc and >1 in CISC

Server Hardware Architecture Performance= 1/ [(cycle Time)x(path length)x(cpi)] To Improve==> Speeding up of the systems Clock Shortening of instruction path length improving the cycles/instruction ratio

Server Hardware Architecture Reduced Instruction Set Computer (RISC) –Contains simplest instruction set extracted from the complex set. The m/c is optimized for these few instructions. Dave Patterson (UCLA) compilers use the simplest set >90%. –Each instruction takes at most one cycle. –Easy to implement Complex Instruction Set Computer (CISC) –Complex instructions- the m/c is optimized for those. It takes longer period to design, debug thus time to market.

Server Hardware Architecture Reduced Instruction Set Computer (RISC) For more than one instruction in a cycle it uses super scalar architecture- splits the processor in separate units, each processor can sustain two or more instructions in a cycle. Instruction cache Branch instruction decode Fix-ProcessFloat-ProcessLogical Proc. Data CacheIO Registers Main Memory

Reduced Instruction Set Computer (RISC) Pipelining -- Internal Parallelism Server Hardware Architecture IDEXMAWBIF

Server Hardware Architecture

Reduced Instruction Set Computer (RISC) A K Stage linear pipeline will offer a K times speedup Steady state in a 5 stage pipeline - five instructions can be executed in one clock cycle.

Server Hardware Architecture Shared Disk (Cluster) Distributed Lock Manager to ensure integrity of data Mutual Exclusion The DLM and Interconnect - Bottleneck for Scalability (4-8 nodes) CPU ME Disk CPU ME Disk CPU ME Disk CPU ME Disk

Server Hardware Architecture Symmetric Multi Processing(SMP) Process can run on any CPU on a machine- share memory (everything) The core structures are accessible to CPUs on a controlled manner Same task may run of multiple CPUs during execution process CPU affinity Memory contention, Bus load - Bottlenecks to scalability CPU ME Disk CPU ME Disk CPU ME Disk CPU ME Disk

Server Hardware Architecture Share Nothing (MPP) CPU ME Disk CPU ME Disk CPU ME Disk CPU ME Disk