The Online Central Tracker of D0 Silvia Tentindo Repond Florida State University at Fermilab (for the D0 Collaboration) 7th International Conference on Advanced Techniques and HEP - Como, 15-19 October 2001 Como,18-Oct-01 Silvia Tentindo Repond

Silvia Tentindo Repond Motivation New Physics !  New Technology : ( new Tev new D0 new trigger , CTT ) Research Discovery Como,18-Oct-01 Silvia Tentindo Repond

Silvia Tentindo Repond Contents Overview ( Physics, Tev, D0 ) The New Central Tracker in the D0 Trigger ( CTT ) : - description of the D0 Trigger components ( CTT components in detail ) - The subDetectors for CTT - The Hardware and the Algorithms of CTT: L1CTT and L2CTT ( L2STT ) Conclusions Como,18-Oct-01 Silvia Tentindo Repond

Silvia Tentindo Repond New Physics : Higgs ! etc Discovery of Higgs at Tevatron is constrained by Luminosity: MH < 107.7 GeV excluded (LEP) For : Run IIa 2fb-1 Run IIb 10 fb1 - >3 s.d. evidence for MH < 180 Gev - >5 s.d. discovery for MH < 120 Gev - exclude SM at 95% CL up to 190 Gev if no Higgs signal 8 fb-1 MSSM SM Como,18-Oct-01 Silvia Tentindo Repond

Silvia Tentindo Repond The Fermilab Tevatron Collider Main Injector (new) Tevatron DØ CDF Chicago  p source Booster TeV collider at Fermilab Peak Luminosity 1032 cm-1s-1( 5X1032 cm-1s-1 ) Energy at CMS 2Tev Integrated Luminosity 2fb-1 ( 8[30?]fb-1 ) Bunch crossing time 396 ns (132ns) Turn-on March 1, 2001 First collisions April 3, 2001 Como,18-Oct-01 Silvia Tentindo Repond

Silvia Tentindo Repond D0 Run II Detector Como,18-Oct-01 Silvia Tentindo Repond

Silvia Tentindo Repond D0 Central Tracker Fiber Tracker Silicon Tracker Forward Preshower Solenoid Central Preshower Como,18-Oct-01 Silvia Tentindo Repond

Silvia Tentindo Repond New D0 for Run II Muon System Upgrades  Enhanced Muon Trigger Excellent Run I Calorimeter  EM and HAD Energy 2 Tesla Magnetic Field  Momentum Scintillating Fiber Tracker  Improved Tracking Silicon Microstrip Tracker  Secondary Vertexing Preshower Detectors  Enhanced EM Identification L1 Central Track Trigger  Selection of Stiff Tracks L2 Impact Parameter Trigger  Identification of Long-Lived Particles Como,18-Oct-01 Silvia Tentindo Repond

D0 Detector Performance Tracking Efficiency - 95% for ||<3 Momentum resolution dpT/pT2=0.002 Vertex reconstruction primary: =15-30m secondary: =35m (r-), 80m (r-z) Lepton ID acceptance muons: pT>1.5 GeV/c, ||<2 electrons: pT>1 GeV/c, ||<2.5 Offline algorithms Como,18-Oct-01 Silvia Tentindo Repond

Silvia Tentindo Repond NewPHYSICS ! ….but … ~ 10 fb b Tagging HIGGS Physics ??? Como,18-Oct-01 Silvia Tentindo Repond

Silvia Tentindo Repond New Trigger ! ! ! Field Programmable Gate Arrays Digital Signal Processors Alpha Processors FPGA DSP Alpha Como,18-Oct-01 Silvia Tentindo Repond

The hardware for the new Trigger FPGAs VME Bus Inputs DSPs Como,18-Oct-01 Silvia Tentindo Repond

Silvia Tentindo Repond Alpha Processor CPU (+fan) PCI-VME Bridge L3 Cache Memory VME Bus PCI Slots Data Switches Magic Bus Main Memory PCI-Mbus PIO Como,18-Oct-01 Silvia Tentindo Repond

Silvia Tentindo Repond D0 CTT Performance + momentum resolution + impact parameter t tbar b bar Como,18-Oct-01 Silvia Tentindo Repond

Trigger Requirements for D0RunII The D0 RunII trigger: Must be flexible Must be fast Must recognize interesting signatures Must select one of ~10**6 events Must have high efficiency and high rejection Dead time must be reduced to minimal Como,18-Oct-01 Silvia Tentindo Repond

Trigger Requirements for D0 RunII The D0 RunII trigger: Is re-programmable Does parallel processing Uses fast devices Uses new algorithms that reliably select interesting signatures These algorithms are sophisticated and able of high rejection Pipelining reduces dead time to minimal FPGAs,DSPs,Alpha’s FPGAs FPGAs Pipeline Como,18-Oct-01 Silvia Tentindo Repond

Run II Trigger System 3 us 100us 100ms L3 L2FW:Combined objects (e, m, j) L1FW: towers, tracks, correlations L1CAL L2STT Global L2 L2CFT L2PS L2Cal L1 CTT L2 Muon L1FPD Detector L1 Trigger L2 Trigger 7 MHz 5-10 kHz CAL FPS CPS CFT SMT FPD 1000 Hz L3 Como,18-Oct-01 Silvia Tentindo Repond

Silicon Microstrip Tracker SMT 240 cm 6 Barrels 12 Disks “F” 4 Disks “H” Read-out: SVX-II chips 800.000 channels Hit resol. 10um, secondary vertex resol. 35um (r,phi) ; 80um(r,z) Como,18-Oct-01 Silvia Tentindo Repond

Silvia Tentindo Repond SMT Barrel Como,18-Oct-01 Silvia Tentindo Repond

Silvia Tentindo Repond Central Fiber Tracker 16.000 channels Read-out: SVX-II chips Fast enough for L1 2.6 m scintillation fibers, VLPC readout + 10m waveguides Mounted on 8 cylinders 20<r<50 cm 8 alternating axial and stereo doublets (2deg pitch) A S Como,18-Oct-01 Silvia Tentindo Repond

Silvia Tentindo Repond Preshower Detectors Central and forward 16.000 + 8.000 channels Extruded triangular scintillator strips with embedded WLS fibers Axial and ±20° stereo layers Refines position and energy measurements of EM showers Reduces electron trigger backgrounds by a factor of 5 Como,18-Oct-01 Silvia Tentindo Repond

Level 3 Global Tracker Real data, Run 2001 Track with 5 fiber tracker hits, 5 3D silicon hits Relative alignment of silicon and fiber trackers verified to 40 m level Como,18-Oct-01 Silvia Tentindo Repond

Central Tracker Trigger : Hardware and Algorithms L1CTT (L2CTT) L2STT Como,18-Oct-01 Silvia Tentindo Repond

Silvia Tentindo Repond Level 1 CTT Axial CFT ( Central Fiber tracker ) and CPS ( central PreShower ) Triggers are integrated : CFT - uses FPGA electronics to perform tracking in 4 pt bins - tracks are then matched to clusters CFT stereo layers are not included CPS stereo layers are not included - not used in L1, processed for readout to L2CPS preprocessor Special boards provide interface to the L2STT preprocessor by distributing the CFT tracks from the octant geometry of CFT to the sextant geometry of SMT Como,18-Oct-01 Silvia Tentindo Repond

Silvia Tentindo Repond Level 1 CTT (cont.) L1 CFT/CPS sends 64 trigger terms to L1 framework, formed from : - Number of clusters without tracks - Number of tracks as function of : Charge Pt bin Association , or lack, with a – high or low – threshold preshower cluster - Occupancy level of the detector - Total pt - Phi sector with highest pt Como,18-Oct-01 Silvia Tentindo Repond

Silvia Tentindo Repond AFE MIX DFE- BC- TM COL- CFT Ax. CPS Ax. L2STT L3 L1CFT /CPS Ax. L3 L2CFT L2PS L1 mT 40 4 75 5 CPS Stereo 20 CFT Stereo. L2FPS L3 L1FPS 16 FPS 32 ·   · 3 · CTT Organization showing links to the L1 TM, L2 PreProcessors and L3 LVDS LINK DAUGHTER CARDS Each filling corresponds to a different flavor TRANSITION CARDS Each color corresponds to a different flavor FSC LINK G LINK LEGEND Created by Manuel I. Martin May. 6, 99 Review October 2001 L2PS L3 CTOC FPSS CTQD STSX STOV CTTT FPTT Como,18-Oct-01 Silvia Tentindo Repond

Silvia Tentindo Repond DFE DaughterBoard for L1CTT trigger Como,18-Oct-01 Silvia Tentindo Repond

L1CTT Tracking Algorithms Trigger response for Z® ee with 4 min.bias Find tracks of particles down to Pt of 1.5 GeV Tag categories (incl. CPS info): track, isolated track, electron, ... A track example Como,18-Oct-01 Silvia Tentindo Repond

Silvia Tentindo Repond L1CTT DFEA Firmware Finds CFT tracks from CFT doublet hits in 4 Pt bin each with 4 sub-bins; In the lowest bin there are ~8,000 track equations Como,18-Oct-01 Silvia Tentindo Repond

Silvia Tentindo Repond L1CTT DFEA Firmware In each Pt bin, track equations are repre-sented as a two dimensional array 44 wide (phi) and 8 tall (±4 sub-bins). + – In the above array, 8 tracks are found, however, only six tracks are reported as follows: Track A is reported. Track B is reported, C is pushed on the stack. Track D is reported Track E is reported, G is pushed on the stack, F is Lost. Track H is reported. Track G is popped from the stack and reported. Stack is then cleared. Como,18-Oct-01 Silvia Tentindo Repond

Silvia Tentindo Repond L2 preprocessor CTT as it is at present is L2CFT; will be substituted by L2STT: receives tracks from L1 CFT - sorts and possibly truncates the tracks before sending to Global Output to Global - tracks sorted by pt - tracks sorted by impact parameter Como,18-Oct-01 Silvia Tentindo Repond

Silvia Tentindo Repond L2 preprocessor STT L2STT uses custom built hardware, but enters standard L2 system through the CFT preprocessor to provide a standard interface to Global receives tracks from L1 CFT Receives hits from SMT Reconstructs clusters and clusters centroids from SMT hits Associates SMT clusters to CFT tracks ( clusters in roads) Fits associated clusters into STT tracks Calculates impact parameter Sends STT tracks to L2Global Sends SMT hits ( axial and stereo) to L3 - improves pt resolution - provides vertex information Como,18-Oct-01 Silvia Tentindo Repond

L2STT Hardware Design CPU 1 2 spare 3 VBD 4 5 6 7 STC 8 9 10 11 12 13 FRC 14 15 16 TFC 20 19 18 17 21 terminator Sector 1 Sector 2 Since most high-pT tracks stay in 30° SMT sector, 12 STT sectors are independent Como,18-Oct-01 Silvia Tentindo Repond

Silvia Tentindo Repond L2STT DaughterBoards L1CTT SMT STC FRC preprocess SMT data find clusters associate clusters with L1CTT tracks L3 TFC L2CTT Como,18-Oct-01 Silvia Tentindo Repond

Silvia Tentindo Repond L2STT Card Flavors fiber road card receive SCL fan out L1CTT data manage L3 buffers arbitrate VME bus silicon trigger card preprocess SMT data associate hits with CFT tracks track fit card fit trajectory to hits CPU initialization downloading monitoring resets VBD Como,18-Oct-01 Silvia Tentindo Repond

Silvia Tentindo Repond TFC Daughter Board of STT Como,18-Oct-01 Silvia Tentindo Repond

L2STT Hit Filtering Algorithm CFT A layer CFT H layer SMT barrels 2-mm road To optimize track-finding efficiency, track purity and execution time, look for hits in all four layers but allow hits in only three out of four layers Como,18-Oct-01 Silvia Tentindo Repond

Silvia Tentindo Repond L2STT Track Fit Card Eight TI DSP processors, each receives 2 CFT hits and r- SMT clusters in road defined by CFT track C program on DSP selects clusters closest to road center at each of 4 layers and performs a linearized track fit: Como,18-Oct-01 Silvia Tentindo Repond

Central Tracker (L2STT) Performance Impact parameter resolution of 35 m includes beam spot size (30 m) SMT resolution (15 m) STT introduces negligible uncertainty to resolution Queuing simulation predicts average STT latency is 25 s with negligible dead-time Como,18-Oct-01 Silvia Tentindo Repond

Silvia Tentindo Repond Conclusions The requirements for new Physics have been addressed by providing a new Accelerator, a new D0 Detector, and a new Trigger System. The most advanced Technology once again has offered and produced the right tools for the HEP Physicists of the new generation to go one step further, in the path of discovery and knowledge. Como,18-Oct-01 Silvia Tentindo Repond

Back to Work ………..and D0 well ! ! ! Como,18-Oct-01 Silvia Tentindo Repond

Silvia Tentindo Repond Appendix Como,18-Oct-01 Silvia Tentindo Repond

The new role of Software in the Trigger Hardware 100 ms “software trigger “(L3) uses sophisticated algorithms, almost identical to the offline reconstruction software . Programmable chips - FPGAs, DSPs and alpha preprocessors - ( L1 and L2 ) use fast versions of such algorithms ( “online algorithms”) on reduced sets of digital information from the detector. 3 us 100 us Como,18-Oct-01 Silvia Tentindo Repond

L2STT SIMULATOR SMT L1CTT L3 L2CTT Tsim_l2stt read SMT hits calculate clusters read L1_CFT roads use filter LUT calculate clusters in road send to TFC L1CTT Tsim_L1stt read CFT tracks order in pt order in overlays make LUTs preprocess SMT data find clusters associate clusters with L1CTT tracks L3 L2stt_fitting read clusters in road LUT to phys coord fit SMT & CFT to track send to L2CTT L2stt_util create LUTs clusters factory hits in road factory tracks factory L2stt_analyze create Ntuples for clusters, roads and tracks L2CTT Como,18-Oct-01 Silvia Tentindo Repond

Silvia Tentindo Repond L2STT SIMULATOR - Roads X vs Y display of Clusters in Roads t tbar + 2 min bias event blue = CFT tracks hit green = SMT Cluster red = Cluster in Road Como,18-Oct-01 Silvia Tentindo Repond

L2STT Emulator - Test vectors SMT L1CTT SMT Test vectors FRC Cluster FPGA --------- STC --------- Filter FPGA Clusters test vectors preprocess SMT data find clusters Roads&Clusters Test vectors associate clusters with L1CTT tracks FRC Test vectors STC Test Vectors TFC Como,18-Oct-01 Silvia Tentindo Repond