1 ATLAS Pixel Sensors Sally Seidel University of New Mexico U.S. ATLAS Pixel Review LBNL, 9 November 2001

2 Features of the Experiment 10-year innermost layer >10 15 cm -2  1-MeV n  ~10 8 channels (1744 sensors) plus spares; want to test these under bias before investing chips on each All of the other subsystems located outside the pixels Impact on the Sensor Design Guarantee stable high voltage; operate below full depletion after inversion. Implement integrated bias circuit. Minimize multiple scattering; minimize mass.

3 Total fluence has been predicted for each component’s lifetime assuming luminosity ramp-up from cm -2 to cm -2 during Years 1-3:

4 Example prediction of depletion voltage versus radius, for 10-year fluence:

5 Simulations were made to select operating temperature and access time:

6 Conclusion: 100 days' 0 °C 30 days' 20 °C 235 days' -10 °C

7 General Features of the Production Sensor Design Rectangular sensors: 2 chips wide x 8 chips long - –Each chip: 18 columns x 160 rows –Each pixel cell: 50 x 400  m 2 –Active area: 16.4 x 60.8 mm 2 n + implants (dose  /cm 2 ) in n-bulk to allow underdepleted operation after inversion Thickness: 250  m

8 Route to the Design First Prototypes - –Designed in ‘97, fabricated by CiS + Seiko, studied in '98-'99 Second Prototypes - –Designed in '98, fabricated by CiS, IRST, and TESLA, studied in ' Pre-production Sensors - –Designed in ' , fabricated by CiS + TESLA, studied in 2001 Production Sensors - –Order in process of release now for delivery to begin in January 2002.

9 The Production Wafer 4-inch diameter, 250  m thick, with: –3 full-size Tiles –6 single-chip sensors –various process test structures to monitor oxide breakdown voltage, flat-band voltage, oxide- silicon interface current, p-spray dose

10 Features of the Full-size Sensors (“Tiles”) Pitch 50 x 400  m cells per sensor Area 18.6 x 63.0 mm 2 Active area 16.4 x 60.8 mm 2 cells in regions between chips are either –elongated to 600  m to reach the nearest chip, or –ganged by single metal to a nearby pixel that has direct R/O

11 Elongation and Ganging of Implants in the Inter-chip Region

12 n-side isolation: p-spray A medium [(3.0 ± 0.5) x /cm 2 ] dose implant applied to the full n-side without masks, then overcompensated by the high dose pixel implants themselves. The p-spray is moderated: it attains a lower boron dose near the lateral p-n junction, thereby reducing the electric field. The surface charge at the junction is optimized at the saturation value (1.5  /cm 2 ) and is slightly higher in the center (3.0  /cm 2 ) for safe overcompensation. The higher dose in the center also reduces the capacitance.

13 Irradiated (2  MeV p/cm 2 ) p-spray sensors: leakage current versus voltage: Irradiated (2  MeV p/cm 2 ) p-stop sensors: leakage current versus voltage:

14 Unirradiated p-spray sensors: breakdown voltage The same sensors irradiated to 9  MeV n/cm 2 : breakdown voltage

15 Breakdown voltage for tile with moderated p-spray (Prototype 2): 410 V Breakdown voltage for tile with normal p-spray (Prototype 1): 180 V

16 Substrate: oxygenated From the ROSE Collaboration: Oxygen- enriched (24 hours in 1150  C environment) silicon is significantly more radiation hard than standard silicon as tested with protons or pions. V dep is 2x lower after /cm 2.

17 The value of oxygenated substrate was confirmed by the ATLAS pixel group: After irradiation to 3  /cm 2 :

18 Guard ring / treatment of the edge –on the p-side: a 17-ring structure of p + implants. Pitch increases with radius. Metal overlaps implant by 1/2 gap width on side facing active area. (See Bischoff, et al., NIM A 326 (1993) ) –on the n-side: no conventional guard ring. Inner guard ring of ~90  m width surrounded by a few micron gap. Region outside gap is implanted n + and grounded externally. Recall that the chip is only a bump’s diameter away. This design guarantees no HV arc from n-side to chip.

19 Bias grid For high yield on assembled modules, we want to test sensors prior to attaching chips - so we want to bias every channel on a test stand without a chip and without contacting implants directly. A bias grid is implemented: –Bus between every pair of columns connects to small n + implant “dot” near each pixel –When bias is applied (through a probe needle) to the grid, every pixel is biased by punchthrough from its dot. –p-spray eliminates need for photolithographic registration, permits distance between n- implants to be small  low punchthrough voltage –Bias grid unused after chips are attached but maintains any unconnected pixels (i.e., bad bumps) near ground

20 Bias Grid

21 Selected mechanical and substrate requirements –thickness  m –thickness non-uniformity, wafer to wafer  m, -30  m –thickness non-uniformity across each wafer - < 10  m –bow -  40  m –crystal orientation - –resistivity k  -cm –resistivity uniformity, wafer to wafer - ±30 % –substrate free of deep levels (C-V independent of frequency f for 20 Hz < f < 10 MHz) –substrate 1150 °C, 24 hrs

22 Selected electrical requirements (measured at 20 °C) –initial operating voltage - 150V or V dep + 50V, whichever is higher –initial leakage V op - < 2  A per tile –current slope at V op - I(V op )/I(V op - 50V) < 2 –initial oxide breakdown voltage -  50V –  I  30% after 30 hours operation in dry air at V op

23 Selected design parameters: –implant spacing  5  m –implant width  5  m –contact hole diameter in oxide or nitride  5  m –contact hole spacing in oxide or nitride  20  m –metal width  8  m –metal spacing  5  m –contact hole diameter in passivation  12  m –contact hole spacing in passivation  38  m –mask alignment tolerance within same side ±2  m –mask alignment tolerance between front and back sides ±5  m

24 Processing parameters: –n + implantation dose > /cm 2 –p-spray effective dose in Si - (3.0 ± 0.5) x /cm 2 –p-side contact dose > /cm 2 Radiation hardness To be tested on 2-4 test structures of 3 types, per batch, after p/cm 2 (CERN PS) and 50 kRad low energy electrons (Dortmund): –V op  600 V –I(600 V) < 100  -10 °C –  I < 30% after °C

25 Pixel sensor testing was done on 120 wafers to reach this design... static studies of irradiated + unirradiated devices test beam studies of sensors with amplifiers. Examples...

26 Static tests Quality assurance procedures assigned a flag Q flag  (-1, 0, +1) to each tile on the basis of its breakdown voltage. Q flag = -1 for 50V < V breakdown Q flag = 0 for 50V < V breakdown < 150V Q flag = +1 for V breakdown > 150V Typical results for CiS (predict production yield):

27 Beam test study of charge collection uniformity track position extrapolated to the pixel detector using strip detector telescope average cluster charge computed for each position bin ~18000e - signal: Track yloc xlc For an oxygenated Prototype 2 V bias = 400 V,  = 5.6  n eq / cm 2 :

28

29 Beam test study of depletion depth Track position from the beam telescope Computed depth of the charge Particle Track

30 After n eq /cm 2, V dep > 227  -600 V for oxygenated substrate

31 Beam test efficiency study V bias = 600 V 98.4% efficiency after  = n eq /cm 2, for 3000e - threshold:

32 Beam Test Study of Spatial Resolution Resolution at 0 o for 3000 e - threshold: depends on ratio (2 hits):(single hits) sharing within ± 3  m ~ 15 % double hits Larger charge sharing region for larger angles Depleted region reduction due to rad damage affects the multiple hits rate Magnetic field modifies charge sharing through Lorentz angle

33 no charge sharing: 1 hits charge sharing: 2 hit 1+2 hits 1 hit 2 hits

34 Beam test study of resolution as a function of azimuthal angle Charge interpolation on the external pixels in the cluster improves spatial precision

35 Analog (Time over Threshold) measurement of the charge improves resolution.

36 Production Sensor Testing Program On all wafers: visual inspection by microscope, before and after all other measurements I-V of every tile, every single chip, and diode with guard ring (for V break ) C-V on diode with guard ring (for V dep ) Once per batch: bow I versus time thickness

37 On a representative sample of control structures, a few per batch: V flat-band, oxide charge, p-spray dose, electron mobility, V break of oxide and nitride layers, inter-pixel resistance, inter-pixel capacitance, implant and metalization resistivities On irradiated test structures: V op, I op,  I vs. time, V break, oxide properties, flat-band voltage, oxide charge, p-spray dose, electron mobility

38 Status the sensors: CiS is approved for full production. Tesla has met specs on unirradiated devices. 25% of their production sensors will be ordered immediately. Final approval for remaining 75% will be given after test beam of irradiated devices next summer. The testing laboratories are ready. QA procedures have been optimized, will be finalized by 7 Dec Production database in use.

39 Sensor Cost Estimate Plan for purchase of the detectors: 2000 tiles required (incl. spares) Order 1/2 from each vendor Both vendors will offer 35% 3-good-tile wafers and 65% 2-good-tile wafers. However present Tesla pricing is based on 50% 3-good/ 35% 2-good so their cost is a conservative estimate. US will pay 20% of total cost.

40 Sensor Cost Estimate, continued CiS: 3-good: 150 wafers  1315 ChF/wafer = ChF 2-good: 275 wafers  840 ChF/wafer = ChF CiS total: ChF Tesla: 3-good: 200 wafers  765 ChF/wafer = ChF 2-good: 200 wafers  383 ChF/wafer = ChF Tesla total: ChF 25% of sensors will be ordered in FY02, 75% in FY03. Total US cost:20%  ChF = $82.2k FY02 US cost: 20%  ChF = $20.6k FY03 US cost: 20%  ChF = $61.7k

41 Sensor Cost Estimate, continued CiS has been approved to provide its full production order. Tesla radiation hardness will be checked after 25% production, and a final decision on Tesla full order will be made in Sept If the full 2000-sensor order reverts to CiS: Total cost increases to ChF = $535k US cost increases to $107k (30% change).

42 Additional costs Needed for FY02 + FY03: 1.0 FTE student tech: $13k/year  2 yr = $26k 0.5 FTE engineer: $36k/year  2 yr = $72k total: $98k

43 Milestones for WBS First outer production wafers delivered18 Jan 02 Outer sensors testing complete31 Jul 03 Outer sensors needed to begin modules 31 Jul 03 First B-layer wafers delivered11 Apr03 B-layer sensors needed to begin modules14 Jul 04