Timing Requirements for Spallation Neutron Sources Timing system clock synchronized to the storage ring’s revolution frequency. –LANSCE: MHz (1/72 of the MHz Acclerator RF frequency) –SNS: Variable MHz. Not derived from the Accelerator RF.

Timing Requirements for Spallation Neutron Sources The end of the cycle is more important than the beginning of the cycle. –Large, high inertia, “T0” neutron choppers define when the beam is extracted from the ring. Most of the other important timing signals (beam and RF gates) end at the “Extraction Time” and derive their starting times by working backwards from the Extraction Time. –Multiple beam lines require multiple choppers to be synchronized by the timing system. –Compromise between keeping a stable “Extraction” reference signal for the choppers and not drifting too far away from the AC line phase for the RF system.

Basic Characteristics of SNS Timing System Event System. –256 events possible. 25 events currently in use. ~5 millisecond machine cycle. 60 Hz. –Option to go to 120 Hz. when second target added. 10 second super-cycle. Clock synchronized with ring RF. –Ring RF is Mz at 1 GeV –Clock is 32 X Ring RF

Timing System Components of SNS Timing System Ring RF Timing Reference Generator Neutron Choppers AC Line SNS Event Link Master X32 PLL (33 MHz) SNS Real Time Data Link Master 10 MHz Crystal Osc. Timing Slave (V124S) Machine Protection System ICS IOC's SNS Utility Module LEBT Chopper *4 PLL (64 MHz) Experimental Halls Diagnostics RTDL Event Link Master Timing IOC SNS Time Stamps Beam data RF Gates Extraction Kickers TxHV Gates High resolution timestamps Machine Modes SNS Timestamps Remote Reset Synchronous ISR’s Beam Delay Beam Phase Micro pulse width Macro pulse width SNS Time stamps Delays Gates Triggers Timing System Hardware Timing System UsersExperimental Systems Subsystem Hardware

Two SNS Transmission Links Event Link –Transmits the timing events that define a machine cycle. –Each event is 8 bits plus parity (256 events maximum). –Clock is variable and derived from the ring revolution frequency (32 * F rev ). –Events 0 – 63 are generated by the timing system hardware. –Events 64 – 255 are generated by software (no fixed times). Real-Time Data Link (RTDL) –Transmits machine parameters and data prior to every new cycle. –128 frames possible (expandable to 255). –Each frame contains an 8-bit frame number, 24-bits of data, and an 8-bit CRC. –Clock is 10 MHz.

Sample SNS RTDL Data Frames Frame NumberData 1 – 3 Time of day 4 Event link period 5 MPS mode 6 60 Hz phase error 7Beam Width 15 IOC Reset Address 17 Pulse Flavor 18-21RF Gate Widths 24 Previous Pulse Status 25 Cycle bit CRC (calculated)

Real-Time Data Link (RTDL) Extract MPS FPAR Event Link End Injection SNS Machine Cycle Timeline 02 ms 1 ms 6 ms4 ms 7 ms 5 ms 8 ms3 ms Anytime Informational Events, non critical timingTime Critical Events, (soft events disabled) RTDL Transmit Snapshot, 1Hz, 6Hz, etc… RTDL Valid RTDL parameter transmission (for next cycle) RF & High Voltage Events MPS FPL System xxx Trigger Events (Alternate) Cycle Start Machine +60 Hz Zero Crossing -60 Hz Zero Crossing Line-Synch Reference Clock Beam On Cycle Start Mostly Stable Triggers Beam On Range Allowed Range for Variable Triggers Extraction Kicker Charge beam accumulation

Basic Characteristics of LANSCE Timing System “Gate” rather than “Event” driven system. 96 independent timing gates  82 gates in use. 8.3 millisecond machine cycle (120 Hz). 1 second super-cycle. Clock synchronized with ring RF. – MHz.

Current Architecture of LANSCE Timing System Star configuration 4 redundant gate generator sets in 2 CAMAC crates. Gate generators are loaded by Master Timer computer, then run independently. Master Timer computer checks the output of the gate generators and automatically switches to another set when a discrepancy is seen. Master Timer MUX Timing Distribution Timing Gates Timing Gate Generators