Design of Digital-to-Analog Converter Qin Chen Yong Wang Dept. of Electrical Engineering Feb. 6th, 2006 EE597G Presentation:

What’s DAC? A device that converts digital signals to analog signals It’s usually used to control analog devices, such as actuator, audio and video output. A/D Digital System D/A Object Ctrl Smpl

Weighted-Resistor DAC – V OUT is a weighted sum of V3, …, V0 with weights proportional to the conductances G3,.., G0. – If X3:0 is a binary number we want conductances in the ratio 8:4:2:1. –Fast: gate slew rate ≈ 3 V/ns. – We can scale the resistors to give the output impedance we want. – Not good for many bits DAC

R-2R Ladder resistances of the two branches at V1 both equal 2R so the current into this node will split evenly. using only two resistor values, can generate a whole series of currents where In=2 n I 0. From the voltage drop across the horizontal resistors, we see that V n = 2RIn = 2 n+1 RI 0. For an N- bit ladder the input voltage is therefore I 0 =2 –N V in /R.

Current-Switched DAC Total current into summing junction is X3:0 ×I 0, Vout = X3:0 × Vin /16R × (–R f ) Use CMOS transmission gates as switches: adjust ladder resistors to account for switch resistance. All the switch output terminals are at 0 V. Ladder outputs are always connected either to ground or to a virtual earth. Advantages: Very fast, No need to charge/discharge node capacitances Only two value resistors can satisfy many bits DAC

Glitches in DAC output voltages Switches in DAC operate at different speeds ⇒ output glitches occur when several input bits change together: 0111->1000 Glitches are very noticeable on a video display:

Deglitching with sample/hold circuit To minimize the effect of glitches: – Use a register to make inputs change as simultaneously as possible – Use a sample/hold circuit to disconnect the DAC output while it is changing

Chip Specifications Resolution: 8 bits No. of channels: 2 Interface: Parallel Output type: Voltage Reference: External Supply voltage: Single, 5V

Chip Specifications (cont.) Power consumption (Max. 200mW) Update rate (100MHz) Settling time (10μs) Area (1mm 2 ) Integral Nonlinearity ( 1 LSB) Differential Nonlinearity (1 LSB)

Chip Diagram Input Latch A DAC A DAC B Input(8 bit) Address Control Input Latch B Address Reference Out A Out B

Project Schedule Week 1Systematic design of chip Week 2Systematic design of chip (cont.) Week 3Circuit design Week 4Circuit design (cont.) Week 5Layout design Week 6Layout design (cont.) Week 7Final adjustments and verification Week 8Final adjustments and verification (cont.)