2006 Work Plan Y. Sugimoto 25-Apr-2006
Study Items Basic study of fully depleted CCD Simulation studies for FPCCD VTX Radiation damage Thin wafer and the support structure Conceptual design of FPCCD for ILC Readout ASIC
Basic study of fully-dep. CCD Charge spread Back-illumination CCD (S deep2) LASER / Fe55 April – May Lorentzs angle From May 8 th – 2 weeks at KEK cryogenic center S deep2 with S5466 as a reference
Simulation studies for FPCCD VTX Background rejection with cluster shape Tracking efficiency with beam background Flavor tagging Vertex charge
Radiation damage study Clock dependence of CTI Using standard CCD irradiated before Electron annealing Verify Nick’s report Using CCDs irradiated with neutron before Irradiate with -source or beam? Radiation damage of fully-depleted CCD Irradiate with -source or beam? Radiation damage of FPCCD When can we get the FPCCD? – Up to HPK
Thin wafer and the support structure Consider 2 options Partially thinned wafer Si-RVC-Si sandwich Simulation with FEA program Measurement of flatness for partially thinned wafer (S deep2) Can we get RVC sample?
Conceptual design of FPCCD Simulation using FEMLAB Discussion with HPK Simulation using ENEXSS-TCAD
Readout ASIC Goal (3 years): 16/32 ch Amp-CDS-ADC with mm pitch System noise < 50 electrons (depends on CCD) 4 – 6 bit 20 Mpix/sec Power: < 10 mW/ch (depends on thermal design of VTX) Target of this year: 1ch sample device Organization Osaka Univ. group is also doing R&D of CP-CCD and the R.O. ASIC for X-ray astronomy Ikeda-san (JAXA) is collaborating with Osaka group for the ASIC Collaboration with Ikeda-san would be efficient for our R&D
R&D Schedule Charge spread /Lorentz angle WS FebMarAprMayJunJulAugSepOctNovDecJanFeb Study of radiation damage Clock v.s. CTI, Damage of full-dep. CCD,etc, B.G. rejection by cls shape Flavor tagging efficiency, etc. Tracking efficiency Machine-time? R&D of r.o. ASIC Thin wafer / Support FPCCD Conceptual design Deadline for proposal to LNS
Funding sources TOKUTEI-KOUBO – “T” KIBAN-(C) – “C” GAKUJYUTU-SOSEI – “G” KEK Annual budget – “A” Basic study of fully depleted CCDC Simulation study for FPCCD VTX for ILCC Radiation damageStandard sizeC, A Fine PixelT, G ElectronicsA, T Thin wafer / support structureC FPCCD conceptual designC, G Readout ASICG
Expected manpower Basic study of fully depleted CCDY.S., K.N., all Simulation study for FPCCD VTX for ILCT.N., PD-A, A.M., PD-B Radiation damageStandard sizeY.S., K.N., PD-B, T.N., PD-A, St-A, and all Fine Pixel ElectronicsK.N. Thin wafer / support structureY.S. FPCCD conceptual designY.S., PD-B Readout ASICPD-A, St-A, K.I. PD-A: Post-doc at Tohoku (Oct.06~) PD-B: Post-doc at KEK (Oct.06~) St-A: Student at Tohoku
Summary We have won satisfactory level of funding for sensor R&D (not enough for all of R&D items of VTX) We have a lot of things to do We now need manpower At least 2 post-docs (Tohoku and KEK) by “GAKUJUTSU- SOSEI” grant We anticipate more post-docs supported by “Postdoctoral fellowships for foreign researchers” of JSPS ( ) We also hope many graduate students to join