16 sept G.-F. Dalla BettaSCIPP Maurizio Boscardin a, Claudio Piemonte a, Alberto Pozza a, Sabina Ronchin a, Nicola Zorzi a, Gian-Franco Dalla Betta b a ITC-irst, Microsystems Division, via Sommarive, Povo di Trento, Italy b DIT, University of Trento, Via Sommarive, 14, Povo di Trento, Italy Development of 3D detectors at ITC-irst

16 sept G.-F. Dalla Betta SCIPP Introduction Single-Type Column 3D detectors Simulation results Technological tests Fabrication of the first batch Preliminary electrical results Conclusion Outline

16 sept G.-F. Dalla Betta SCIPP Introduction ITC-irst is developing the process for the fabrication of 3D sensors. Framework: RD50 collaboration - for the development of radiation tolerant detectors INFN-PAT agreement We have started with a simplified process, since all necessary clean-room equipment is not available yet

16 sept G.-F. Dalla Betta SCIPP “Standard” 3D detectors - concept First 3D architecture, proposed by S.I. Parker et al. [1] in 1997: columnar electrodes of both doping types n-columns p-columns wafer surface ionizing particle Short distance between electrodes: low full depletion voltage short collection distance more radiation tolerant than planar detectors!! n-type substrate [1] S.I. Parker et al., Nucl. Instr. Meth. Phys. Res. A 395 (1997) 328 DRAWBACK: Fabrication process rather long and not standard, so mass production of 3D devices very critical and very expensive.

16 sept G.-F. Dalla Betta SCIPP “Standard” 3D detectors - fabrication Kenney et al. IEEE TNS, vol. 46, n. 4 (1999) 1) wafer bonding support wafer detector wafer 2) n+ hole definition and etching resist oxide 3) hole doping and filling n+ polysilicon 4) p+ hole definition and etching resist 5) hole doping and filling p+ polysilicon 6) Metal deposition and definition metal

16 sept G.-F. Dalla Betta SCIPP Single-Type-Column 3D detectors - concept Sketch of the detector: grid-like bulk contact ionizing particle cross-section between two electrodes n+n+ n+n+ electrons are swept away by the transversal field holes drift in the central region and diffuse towards p+ contact n-columns p-type substrate Etching and column doping performed only once Functioning:

16 sept G.-F. Dalla Betta SCIPP 3DSTC detectors - concept (2) Further simplification: not passing-through holes p-type substrate n + electrodes Uniform p+ layer Bulk contact is provided by a Backside uniform p+ implant single side process. No need of support wafer.

16 sept G.-F. Dalla Betta SCIPP TCAD Simulations - static (1) 3D simulations are necessary DEVICE3D tool by Silvaco Important to exploit the structure symmetries to minimize the region to be simulated n+n+ cell 50  m p-type substrate Wafer thickness: 300  m Holes: 5  m-radius 250  m-deep

16 sept G.-F. Dalla Betta SCIPP TCAD Simulations - static (2) Potential distribution (vertical cross-section) 0V -10V -5V 50  m 300  m Potential distribution (horizontal cross-section) null field regions -15V

16 sept G.-F. Dalla Betta SCIPP TCAD Simulations - static (3) Potential and Electric field along a cut-line from the electrode to the center of the cell To increase the electric field strength one can act on the substrate doping concentration Na=1e12 1/cm 3 Na=5e12 1/cm 3 Na=1e13 1/cm 3 Na=1e12 1/cm 3 Na=5e12 1/cm 3 Na=1e13 1/cm 3

16 sept G.-F. Dalla Betta SCIPP TCAD Simulations - dynamic (1) Current signal in response to an ionizing particle. Vertical tracks in 3 different positions Electron cloud evolution (b) n+n+ n+n+ n+n+ n+n+ a b c

16 sept G.-F. Dalla Betta SCIPP TCAD Simulations - dynamic (2) Case b. Case c. Nsub=1e12 cm -3 Nsub=5e12 cm -3 Nsub=1e13 cm -3 Nsub=1e12 cm -3 Nsub=5e12 cm -3 Nsub=1e13 cm -3 1ns 10ns Current (A) In the worst case the induced current peak is within 10ns For a hit 5  m from the electrode the peak is within 1ns.

16 sept G.-F. Dalla Betta SCIPP TCAD Simulations – critical points evidenced Long low tail in the current signal due to hole diffusion. Simulation have shown that this effect can be strongly minimized using passing-through electrodes. High electric field at the bottom of the hole. Anyway we should not reach critical values because of the low bias voltages needed. In case of p-spray isolation, high electric field at the column/p-spray junction. Again, may be of concern depending on the bias voltage needed.

16 sept G.-F. Dalla Betta SCIPP Technological tests - lithography as-deposited: Photoresist tends to penetrate inside the hole forming a thicker layer in these region after exposure and development: residual photoresist in the hole region Important to note that resist can be defined in the proximity of the hole. The resist trapped in the hole is removed after the process

16 sept G.-F. Dalla Betta SCIPP Technological tests - deposition SurfaceTopbotton Poly1m1m0.8  m0.7  m TEOS1m1m0.7  m0.6  m Poly and oxide deposition top bottom hole surface oxide poly oxide

16 sept G.-F. Dalla Betta SCIPP Technological tests – oxide growth Oxide Growth (500nm) in a 5  m diameter hole metal oxide hole top bottom

16 sept G.-F. Dalla Betta SCIPP hole Aluminum does not penetrate inside the hole contacts have to be made on the wafer surface aluminum Technological tests – metal sputtering

16 sept G.-F. Dalla Betta SCIPP initial oxide p + -doping of back Isolation: p-stop or p-spray masking for deep- RIE process deep-RIE (CNM, Barcelona-Spain) Fabrication process (1) oxide p-stop p + doping holes

16 sept G.-F. Dalla Betta SCIPP P-diffusion (no hole filling) Oxidation (hole passivation) Opening contacts Metal and sintering Fabrication process (2) P- diffused regions Hole passivation contacts metal

16 sept G.-F. Dalla Betta SCIPP Mask layout Small version of strip detectors Planar and 3D test structures “Low density layout” to increase mechanical robustness of the wafer “Large” strip-like detectors

16 sept G.-F. Dalla Betta SCIPP Mask Layout-Test structures 3D-Diode Pitch 80 µm 10x10 matrix Ø hole 10 µm 44 holes GR Standard (planar) test structures

16 sept G.-F. Dalla Betta SCIPP layout - strip detectors Mask layout - strip detectors metal p-stop hole Contact opening n+n+ AC and DC coupling Inter-columns pitch  m Two different p-stop layouts Holes Ø 6 or 10  m Inner guard ring (bias line)

16 sept G.-F. Dalla Betta SCIPP Fabrication run: main characteristics Substrate: Si High Resistivity, p-type,  FZ (500  m)  >5.0 k  cm  Cz (300  m)  >1.8 k  cm Wafers with lower resistivity are not easy to find Surface isolation:  p-stop  p-spray

16 sept G.-F. Dalla Betta SCIPP SEM micrographs Portion of a strip detector Top-side of a column strip Column-section 100  m 6  m metal oxide

16 sept G.-F. Dalla Betta SCIPP Electrical Characterization (1) Different sub-types and thicknesses 2% to 13% variation on single wafer Ileak measured below full depletion due to breakdown Standard (planar) test structures electrical parameters compatible with standard planar processes DRIE does not endanger device performances

16 sept G.-F. Dalla Betta SCIPP Electrical Characterization (2) IV measurements 3D-Diode P-stop P-spray I leak 20V 0.67 ±0.12 pA I leak 20V 0.33 ±0.24 pA CZ FZ diode ─ guard ring 10x10 matrix Ø hole 10 µm Pitch 80 µm Active area ~0.64 mm 2 diode ─ guard ring

16 sept G.-F. Dalla Betta SCIPP >50 I bias line [nA] Detectors count Electrical Characterization (3) Strip detectors Current 40V of 70 different devices 1detector: 230 columns x 64 strips on 1 cm 2 ~ columns average current per column < 1pA Good process yield FZ

16 sept G.-F. Dalla Betta SCIPP Conclusions A new type of 3D detector has been conceived which leads to a significant simplification of the process: hole etching performed only once no hole filling no wafer bonding First production is completed: Good electrical parameters (DRIE does not endanger device performance) Low leakage currents 100V for p-stop in 3D diodes Good yield for strip detectors (Current/hole < 1pA/column for 93% of detectors) Accurate analysis of CV measurement results is in progress with the aid of TCAD simulations …

Lateral depletion-voltage Preliminary “3d-diode”/GR capacitance measurements C int - Vback Weak capacitive coupling at very low voltages (conductive substrate layer between columns) ~ 5V lateral full depletion voltage (100µm pitch) Vback Capacitive coupling between 40 columns (100um=pitch, 150um depth) C int

Backplane full-depletion-voltage Preliminary “3d-diode”/back capacitance measurements C-V 1/C 2 -V Lateral depletion contribution to measured capacitance at low voltages Linear 1/C 2 vs V region corresponding to the same doping level of planar diodes Saturation capacitance corresponding to a depleted width of ~ 150µm)  Column depth ~ 150µm ~ 40V full depletion voltage (300µm wafer)