The New Single-silicon TFTs Structure for Kink- current Suppression with Symmetric Dual-Gate by Three Split Floating N+ Zones Dept. of Electrical Engineering, Korea Univ. Dae Yeon Lee Supervised by Man Young Sung (Korea Univ.)

Semiconductor & CAD Lab. Dae Yeon Lee 2 Contents Introduction Background Proposal Simulation & Results Conclusion

Semiconductor & CAD Lab. Dae Yeon Lee 3 Introduction  The Conventional Single-Gate TFT * High On-current * High Electric Field at the Channel/Drain Junction * Kink-Effect Premature Breakdown !  The Conventional Dual-Gate TFT * Low On-current * Low Electric Field at the Channel/Drain Junction * Stable I-V Characteristic by Kink-Effect Suppression Goal is the Mixing of The Merit the each two TFTs 1. Kink-Effect Suppression 2. Improved On-Current High On-Current Reduction of Kink-Effect +

Semiconductor & CAD Lab. Dae Yeon Lee 4 Back Ground  Lowering the Electric Field by having Dual-Gate Structure Lowering the Impact Ionization at the Channel/Drain Junction Lowering the Generated Holes flowed to Source/Channel Junction Floating N+ region recombines with the Holes Defense the lowering the Electrostatic Potential Barrier at the Source/Channel Junction by the Holes Proposed TFT structure achieved the reduction of the Kink-Effect so that stable Drain Current in the Saturation Region Defense PBT action Parasitic Bipolar Transistor

Semiconductor & CAD Lab. Dae Yeon Lee 5 Proposal  The Dual-Gate TFT with Floating N+ channel oxide Gate SourceDrain N+ 16um 400nm 3um 100nm 1um 1.65um Mo 1um 1.65um 0.7um 700nm 110nm N+ 2um Total channel length=10um 400nm P P PP N+ - Off-Set Region Electrons inject at the Forward Bias Middle N+ region length < 1.51 um Lowering the Electric Field

Semiconductor & CAD Lab. Dae Yeon Lee 6  Design Rules

Semiconductor & CAD Lab. Dae Yeon Lee 7 Simulation & Results  Electrostatic Potential  Hole concentration  Electric Field  Drain Current – Drain Voltage Output Characteristics  Output Conductance

Semiconductor & CAD Lab. Dae Yeon Lee 8  Electrostatic Potential Conventional Dual-gate TFT Proposed Dual-gate TFT Conventional Single-gate TFT V G = 7 V, V D = 12 V  Lowering potential barrier at the source causes the kink effect.  Proposed TFT’s potential barrier enhanced the potential barrier 5 times than Single - gate TFT and enhanced 18 % that of conventional dual-gate TFT.

Semiconductor & CAD Lab. Dae Yeon Lee 9  Electrostatic Potential (Zoom In) V G = 7 V, V D = 12 V  The channel region starts from 4.3 um point  The Potential Barrier value for the each TFTs Value is 0.5 V, 2.3 V, 2.8 V at a 5 um point which starts floating n+ region Source Channel

Semiconductor & CAD Lab. Dae Yeon Lee 10  Hole Concentration Conventional Single-gate TFT Conventional Dual-gate TFT Proposed Dual-gate TFT >  High Electric field at Drain Junction causes Impact Ionization so that holes flow to the source junction through channel -> PBT action  Floating N + regions recombine with holes so that hole concentration at the source junction can be reduce. V G = 7 V, V D = 12 V

Semiconductor & CAD Lab. Dae Yeon Lee 11  Hole Concentration (Zoom In) V G = 7 V, V D = 12 V  The channel region starts from 4.3 um point  The Hole concentration value for the each TFTs Value is /cm 3, 10 1 /cm 3, /cm 3 at a 5 um point which starts floating n+ region Source Channel

Semiconductor & CAD Lab. Dae Yeon Lee 12  Electric Field Conventional Single-gate TFT Conventional Dual-gate TFT Proposed Dual-gate TFT  High Electric field at Drain Junction causes kink effect.  The usual approach to reduce this effect is to limit the impact ionization contribution decreasing the electric field at the drain junction. V G = 7 V, V D = 12 V

Semiconductor & CAD Lab. Dae Yeon Lee 13  Electric Field (Zoom In) V G = 7 V, V D = 12 V  The channel region starts from 12.9 um point  The electric field value of each TFT is approximately 10 5 V, 2.8×10 2 V, and 2.9×10 2 V. Channel Drain

Semiconductor & CAD Lab. Dae Yeon Lee 14  Drain Current – Drain Voltage Output Characteristics mA mA  The on-current of the proposed dual-gate TFT is mA while that of the conventional dual-gate TFT is mA  This result shows a 67 % enhancement in on-current mA V G = 7 V, V D = 12 V

Semiconductor & CAD Lab. Dae Yeon Lee 15  Drain Current – Drain Voltage Output Characteristics Conventional Single-gate TFT Conventional Dual-gate TFT Proposed Dual-gate TFT V G =5 V V D =10V mA0.325 mA0.508 mA V G =5 V V D =12V mA0.330 mA0.522 mA V G =7 V V D =10V mA0.508 mA0.862 mA V G =7 V V D =12V mA0.522 mA mA W/L = 2

Semiconductor & CAD Lab. Dae Yeon Lee 16  Drain Current – Drain Voltage Output Characteristics  The on-current of the proposed dual – gate TFT at different gate voltage

Semiconductor & CAD Lab. Dae Yeon Lee 17  Output Conductance Characteristics Kink starting point V G = 7 V, V D = 12 V  Reduction of the Output conductance means the reduction of the kink effect so that we can get a stable drain current in the saturation region.  The output conductance of the conventional single-gate increases about 8.3 V.

Semiconductor & CAD Lab. Dae Yeon Lee 18 Conclusion  Lowering the High electric Field at the Drain junction by Dual – Gate TFT structure  Improved Electrostatic Potential  Reduction of the Hole concentration by the holes recombine with the Floating N+ region in the channel region  On-Current is mA in the saturation region while that of the conventional dual – gate TFT is mA at V G = 7, V D = 12 V  A stable Output Conductance is accomplished by the reduction of the kink effect