Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building Yanfeng Wang, Qiang Zhou, Xianlong Hong, and Yici Cai Department of Computer Science and Technology, Tsinghua University, Beijing ISCAS 2007

Outline Introduction Previous Works Algorithm Dynamic Clock-Tree Building Multi-Level Attractive Force Experimental Results Conclusions

Introduction Clock network can consume as much as 40% of entire chip power budget due to its huge fanout size and high frequency of switching The huge current drawn by clock network contributes considerably to power supply noise which is a major source of variations

Introduction (cont.) Minimizing clock network size/wirelength can lead to Reduced power consumption Less power supply noise Less # buffers Less vulnerability to variations Clock Wirelength vs. Signal Wirelength Give vary large weight to the clock net (X) Pull all the registers together very close to the center of the chip (X)

Previous Works Traditionally, minimization is handled by clock routing using clock-tree building The improvement may be limited if the input register placement is poor Impose geometry constraints for the location of the registers may be too strong for the placement Set up a referential H-tree structure before the placement, and attach registers to the leaf nodes of the H-tree and fix them ([2], [3])

Registers Clumping [6] “Power-Aware Placement” The net-switching power can be modeled by the formula: kV 2 fC Registers Clumping is to reduce the capacitance C of the clock tree Groups registers into clusters Clumps the registers in the same cluster closer to each other

Pseudo Clock-Tree Most emphasis should be placed on local branches of the tree Pseudo Clock-Tree Construction Choose 2 closest registers or middle nodes that are in the same level Add the middle node to be their parent Insert a hyper edge to connect them

Pseudo Clock-Tree (cont.) Advantages of pseudo clock-tree By controlling the middle nodes, we can pull the registers towards any improvement direction The influence of high level nodes on leaf level nodes is not apparent  The effect on the registers mainly comes from the local branches

Force-Directed Placement Reducing the placement problem to solving a set of simultaneous linear equations to determine equilibrium locations for cells Iteration Select and fix one cell to its zero-force location Spread other cells that don’t satisfy the constraints

Dynamic Clock-Tree Building The pseudo clock-tree should be destroyed and rebuilt several times

FDP Combined with DCTB After the initial placement, build the pseudo clock-tree Add extra forces (Multi-Level Attractive Forces) and combine them with the original forces of FDP After every definite times of loop, rebuild the pseudo clock-tree

Multi-Level Bounding Box It’s suitable for local branches of the clock- tree To make the bounding box small, 2 schemes 1: Contract anyone of its two children boxes 2: Make those two children boxes closer

Multi-Level Attractive Forces A kind of “soft adjustment” to more instance To contract the bounding box corresponding to the branch rooted by N1 Scheme 1: Add force on R1 and R2 (or R3 and R4) Scheme 2: Add force on N2 and N3

Experimental Results After placement, use the UST clock router [7] running in the zero-skew mode to compute the clock net wirelength

Experimental Results (cont.)

Conclusions They proposed a method that can reduce the clock net wirelength and preserve the traditional placement wirelength How the values of added forces come from is not mentioned How about power reduction?