Robert Szczygieł IFJ PANSPIE 2005 Radiation hardness of the mixed-mode ASIC’s dedicated for the future high energy physics experiments Introduction Radiation hardness of ABCD - the readout chip for silicon strip detectors Radiation hardness of DTMROC - the readout chip for straw tube detectors Conclusions

Robert Szczygieł IFJ PANSPIE 2005 Introduction High Energy Physics experiments require radiation hard mixed-mode and digital ASICs for fast detector data processing. ATLAS detector – 150 mln sensors to be read out every 25 ns.

Robert Szczygieł IFJ PANSPIE 2005 ATLAS – one of the experiments build on LHC. Introduction Pixel sensors: mln Silicon strips: mln Straw sensors: mln Radiation up to 134 Mrad and 2.3·10 15 n eq /cm 2 for 10 years of operation

Robert Szczygieł IFJ PANSPIE 2005 Introduction Radiation effects in semiconductor devices - TID Total irradiation dose (TID) effects – charge accumulation in SiO 2 and at the Si/SiO 2 interface, new interface states, new recombination centers MOS threshold voltage shift carrier mobility degradation leakage currents - device and chip level bipolar transistor ϐ degradation transistor noise increase increased parameters' spread (important in multichannel ASIC's) At the circuit level: analogue parameters (gain, BW, offset, etc.) are modified, reduced digital logic speed, changed power consumption.

Robert Szczygieł IFJ PANSPIE 2005 Introduction Radiation effects in semiconductor devices - SEE Single event effects (SEE) – charge generated by single particle single event transients (SET) in combinational logic single event upset (SEU) in memory elements single event gate rupture (SEGR) single event burnout (SEBO) The SEE lead to functional errors or device destruction. Radiation effects depend on: technology type of radiation device biasing temperature

Robert Szczygieł IFJ PANSPIE 2005 Introduction Submicron technologies. MOS transistors' V th shift negligible due to the charge removal from the gate oxide (tunneling effect). Leakage currents in NMOS transistors still important. Leakage currents can be eliminated by using enclosed layout transistors. Drawbacks: increased size, limited W/L ratio

Robert Szczygieł IFJ PANSPIE 2005 Introduction Requirements for readout ASIC's in the ATLAS Radiation hard – should work reliably for 10 years in highly radioactive environment ( times higher than for space) Low power – cooling systems introduced in the detector volume disturb the particle traces Minimal area – granularity of the sensors in the tracking detectors is very high Multichannel – providing data processing for a number of sensors Functionality – should provide data compression via trigger system (store all the data from the sensor until the validating “trigger” signal arrives)

Robert Szczygieł IFJ PANSPIE 2005 ABCD chip ABCD – silicon strip detectors readout Fast front-end: 20 ns peaking time Low noise: pF CL Clock: 40 MHz Data retention: 3.2 µs 6.4 mln channels in the system. Power: < 0.5 W Area: 51 mm 2 Transistors: TID: 10 Mrad 2·10 14 n eq /cm 2

Robert Szczygieł IFJ PANSPIE 2005 ABCD chip ABCD Radiation hardness radiation hardened 0.8 µm BiCMOS SOI technology; ELTs not necessary, low number of SEE programmable biasing for analogue channels and internal calibration DACs for discriminator threshold correction in all 128 analogue channels speed margins for digital logic (expected 100 % slow down after irradiation) precise internal synchronization by analogue simulations redundant clock and data inputs bypassing scheme

Robert Szczygieł IFJ PANSPIE 2005 ABCD chip Bypassing scheme Any damaged chip in the module can be bypassed.

Robert Szczygieł IFJ PANSPIE 2005 ABCD chip Two different types of memories used (result of power/area optimization) -> impossible to balance the clock tree on the chip level -> analogue simulations for all the corners (10 sets of irradiation models) ABCD internal synchronization

Robert Szczygieł IFJ PANSPIE 2005 ABCD chip ABCD irradiation tests 24 GeV proton beam, CERN PS 200 MeV pions, PSI Villingen neutrons, nuclear reactor at Ljubljana 10 keV X-rays, CERN Test results no catastrophic failures analogue channels biased properly increased noise in the analogue channels increased channel threshold spread, corrected with DACs digital logic working at speed > 40 MHz logic speed down by a factor of ~2 SEU rate negligible comparing to noise ABCD fulfills the ATLAS Semiconductor Tracker specification.

Robert Szczygieł IFJ PANSPIE 2005 DTMROC chip DTMROC – straw tube detectors readout Clock: 40 MHz TID: 7 Mrad 3.5·10 14 n eq /cm channels in the system. Area: 26 mm 2 Data retention: 6.4 µs Transistors:

Robert Szczygieł IFJ PANSPIE 2005 DTMROC chip DTMROC Radiation hardness submicron 0.25 µm CMOS technology; negligible MOS V th shift (15 mV NMOS, -30 mV 10 Mrad) enclosed layout transistors (ELT) in analogue and digital part (dedicated standard cell library) triplicated control logic and registers with SEU counter parity checking for all the registers watchdog circuits DLL monitoring command decoder designed to accept any input data; it rejects any invalid input data and recovers after predefined time to minimize the probability of loosing the synchronization with the rest of the system

Robert Szczygieł IFJ PANSPIE 2005 DTMROC chip SEU protection areas in DTMROC Only the parts of the logic necessary for keeping the data processing efficiency within the experiment specification are protected.

Robert Szczygieł IFJ PANSPIE 2005 DTMROC chip Triplicated 1-bit register with self-recovery and SEU output V. Ryjov

Robert Szczygieł IFJ PANSPIE 2005 ABCD chip DTMROC irradiation tests 1.33 MeV gamma (Co-60), Saclay 24 GeV protons, CERN PS neutrons, reactor in Ljubljana 60 keV X-ray, CERN Test results 10 % DAC range increased, no linearity degradation no speed degradation power consumption not modified SEU in critical parts eliminated by redundancy SEU crossection in the registers ·10 14 cm 2 DTMROC fulfills the ATLAS Transition Radiation Tracker specification.

Robert Szczygieł IFJ PANSPIE 2005 Conclusions 1. ASIC's dedicated to the readout of the tracking detectors in future HEP experiments have to be characterized by low power, fast data processing and very high radiation hardness. 2. The radiation hardness of the ASIC's is achieved by using the radhard or submicron technology and dedicated design elements. 3. Radhard design has been demonstrated on the examples of two chips, ABCD and DTMROC. 4. Both ASIC's fulfill the specifications. They have been produced, and are being installed in the ATLAS experiment.

Robert Szczygieł IFJ PANSPIE 2005 Conclusions Francis Anghinolfi Gerit Meddeler Daniel Lamarra Władysław Dąbrowski Jan Kapłon Vladimir Ryjov Mitch Newcomer Nandor Dressnandt Rick Van Berg Paul Keener Henry Williams Tor Ekenberg Thanks to ABCD and DTMROC design teams: