Project Characterization Implementing a compressor in software and decompression in hardware Presents by - Schreiber Beeri Yavich Alon Guided by – Porian Moshe

Intro 142 ❤ Compressed data (Wireless) Gym 132 ❤ 170 ❤ 79 ❤ 130 ❤ 127 ❤ Gym Control Room

Intro (Cont.) Problem Data transmission time Processing time Complex layout

Solution Transmitter Compresses the data Receiver extracts and displays the data Intro (Cont.)

Project’s goal Implement a software compressor with a hardware extractor. ◦ Compressor -> Matlab ◦ Extractor -> FPGA

Algorithm Run Length Transmit Value & Repetitions

Algorithm -simple Example Picture pixel’s Values: Transmitted data : repetitionvalue

Project’s requirements 1. Input of 640*480 picture resolution. 2. Programming “Run length algorithm” in Matlab, using it as the compressor. 3. Creating a data array from the algorithm’s output and wrapping it in a pre determined packet. 4. Sending the packet to the FPGA through serial communication using RS-232 protocol.

5. Checking the compressed data in the FPGA for errors with a pre determined CRC. 6. Storing the compressed data to an external memory - SDRAM 7. Implementation of the extractor within the FPGA using VHDL. 8. Presenting the extracted data on display with VESA protocol. Project’s requirements (Cont.)

Project’s requirements Picture to be compressed (640x480) Displayed Picture (800x600) HOST VGA DE2 Board

Message Pack Structure SOF Type Address Data Length Data (Payload) CRC EOF 8 bits 1 Byte 3 Bytes 1 Bytes Up to 1 Kbytes (2 SDRAM’s full page) 1 Bytes

TOP ARCHITECTURE

VGA Display Host Matlab UART RXP UART TXP Message Decoder RAM MUX Message Encoder RAM DEC Display Controller RunLen Decoder CRC IS42S16400 SDRAM SDRAM Controller Arbiter Mem Write Mem Read REGISTERS Packet TX Packet RX Ext. Clk PLL Reset D’ bouncer Reset D’ bouncer Ext. Reset Sys. Clk Sys. Rst FPGA – Cyclone II TX RX VESA 115,200KBit/sec 800x600

Matlab GUI (debug version) Compression TimeCompression Ratio

Compressed Data Example Compressed: Decompressed:

MICRO ARCHITECTURE

DATA Addr DATA COLOR DATA VALID Message Decoder RAM DEC Mem Write Arbiter SDRAM Controller Mem Read RunLen Decoder REGISTERS VGA Display TX PACK PLL Reset Debouncer Resets SDARM UART Matlab UART RXP RAM Controller Display Controller FIFO (dual clock) FIFO (dual clock) UART TXP REG Controller Addr REG TYPE REG CRC RX REG CRC CLC REG Len REG CMP UART RXD UART TXD from UART TX VALID DATA REG CRC STATUS ISEOF FROM MSG_DEC MP REGS RESET FROM MSG_DEC RESET TO CMP REQ Byte_in_pack VALID ISEOF FROM MSG_DEC DATA WREN WR_addr RD_adress Type DATA REQ EN REQ ACK REQ Adress ACK VALID DATA RX_RDY to MEM READ RX_RDY from MEM READ DATA_RDY to MEM READ DATA_RDY from MEM READ REP VALID DATA COLOR COL_EN DATA RGB UART TXD to UART TX 50MHZ 40MHZ (VESA) 133MHZ (SDRAM, System – optional ) 80MHz (System - optional) 1 bit 8 bits 10 bits 16 bits 22 bits Line legend Data & Control MSG_OK Num Pixels n_pix 40MHz

Schedule To do…DateNum. Theoretical self-instruction1.10 – Run length algorithm implementation17.10 – SDRAM Controller implementation24.10 – Architecture definition31.10 – Project Characterization presentation Full characterization of all blocks Implement UART RX-MP & TB Implement UART TX-MP & TB Prepare Mid. Presentation

Schedule To do…DateNum. Implement Display Controller & TB Implement RAM controller & TB Exams!!! Prepare documentation to existing models, end of semester presentation, and final semester A report Present end of semester presentation23.213