Design of Digital-to-Analog Converter Qin Chen Yong Wang Dept. of Electrical Engineering Mar. 14th, 2006 EE597G Presentation:

Outline CMOS switch design and simulation Challenge and Solution R-2R Voltage DAC Schematic design and simulation results Chip Specifications Project Progress

CMOS Switch Circuit

Turn on resistance Control signal is high: When Vin<Vdd-Vgs1, M1 is turned on; When Vgs2<Vin<Vdd, M2 is turned on; The total parallel resistance make the turn-on resistance always low at the whole voltage range.

Simulation Results VG=0V, RL=10k Ohm VG=+5V, RL=10k Ohm

Challenge For R-2R current DAC, how to change virtual ground to 2.5V in CMOS circuits? How to get rid of glitches? How to implement large resistors (>10k ohm) in layout? [next step]

Glitches in DAC output voltages Switches in DAC operate at different speeds ⇒ output glitches occur when several input bits change together: 0111->1000 Glitches are very noticeable on a video display:

Voltage-Mode R-2R Network DAC

Advantages and Disadvantages of Voltage R-2R DAC Advantages: the constant output impedance, which eases the stabilization of any amplifier connected to the output node. No glitch, switch the arms of the ladder between low impedances, capacitive glitch currents tend not to flow in the load. Disadvantages: operate over a wide voltage range (VREF to GND). This is difficult from a design and manufacturing viewpoint gain of the DAC cannot be adjusted by means of a resistor in series with the VREF terminal.

D9-D0: 10,0000,0000 Vref: +5V

Linear output characterization

Testing the op amp

Freq. Response of Gain & Phase

Compensation

Compensation result

Output buffer

The output curve of output buffer

Voltage Reference

Characteristics of voltage reference R load ( Ω )5K (I) 10K (I/2) 40K (I/8) 160K (I/32) 5M (I/1024) Open V out (V) V + ─ Vout=2.5V 5V 20K R load

Building the DAC

Test the DAC

Test result of DAC

What have been done OP Amp design and simulation CMOS switch design and simulation Schematic adjustment Schematic circuit design and simulation

Project Progress =>> Week 1Systematic design of chip Week 2Systematic design of chip (cont.) Week 3Circuit design Week 4Circuit design (cont.) Week 5Layout design Week 6Layout design (cont.) Week 7Final adjustments and verification Week 8Final adjustments and verification (cont.)