Anshul Kumar, CSE IITD CSL718 : Pipelined Processors  Types of Pipelines  Types of Hazards 16th Jan, 2006

Anshul Kumar, CSE IITD slide 2 Types of Pipelined processors Degree of overlap –Serial, Overlapped, Pipelined, Super-pipelined Depth –Shallow, Deep Structure –Linear, Non - linear Scheduling of operations –Static, Dynamic

Anshul Kumar, CSE IITD slide 3 Degree of overlap Depth Serial Overlapped Pipelined Shallow Deep

Anshul Kumar, CSE IITD slide 4 Pipeline Structure ABC Non-linear Pipeline ABC Linear Pipeline Sequence: A, B, C, B, C, A, C, A

Anshul Kumar, CSE IITD slide 5 Scheduling/timing alternatives Static –same sequence of stages for all instructions –all actions in order –if one instruction stalls, all subsequent instructions are delayed Dynamic –above conditions are relaxed –higher throughput is achieved

Anshul Kumar, CSE IITD slide 6 Dynamic Scheduling type 1 : beginnings (decode) and endings (put away) in order type 2 : only beginnings in order type 3 : no order restrictions except dependencies type 1 extended : beginnings in order, references that effect memory state are in order [note that a memory reference may lead to page fault]

Anshul Kumar, CSE IITD slide 7 Pipelining and CPI

Anshul Kumar, CSE IITD slide 8 Hazards in Pipelining Data dependencies => Data hazards –RAW (read after write) –WAR (write after read) –WAW (write after write) Resource conflicts => Structural hazards –use of same resource in different stages Procedural dependencies => Control hazards –conditional and unconditional branches, calls/returns

Anshul Kumar, CSE IITD slide 9 Data Hazards delay = 3 previous instr current instr read/write

Anshul Kumar, CSE IITD slide 10 Structural Hazards Use of a hardware resource in more than one cycle Different sequences of resource usage by different instructions Non-pipelined multi-cycle resources ABAC ABAC ABAC ABCD ACBD FDXX FDXX Caused by Resource Conflicts

Anshul Kumar, CSE IITD slide 11 Control Hazards delay = 5 branch instr next inline instr target instr cond eval delay = 2 the order of cond eval and target addr gen may be different cond eval may be done in previous instruction target addr gen

Anshul Kumar, CSE IITD slide 12 Handling Data Hazards previous instr current instr W R EX Data Forwarding previous instr current instr W R Instruction Reordering 1 2

Anshul Kumar, CSE IITD slide 13 Analysis of Structural Hazards ABC Non-linear Pipeline Reservation Table for X

Anshul Kumar, CSE IITD slide 14 Analysis of Structural Hazards ABC Multi-functional Pipeline Reservation Table for X Y Y Y Y Y Y for Y

Anshul Kumar, CSE IITD slide 15 Collisions with Initiation Interval =2

Anshul Kumar, CSE IITD slide 16 Collisions with Initiation Interval =5

Anshul Kumar, CSE IITD slide 17 Latency Sequences and Cycles 1, 8, 1, 8, ….(1, 8)avg = 4.5 3, 3, 3, 3, ….(3)avg = 3 6, 6, 6, 6, ….(6)avg = 6 Minimum Average Latency (MAL) ?

Anshul Kumar, CSE IITD slide 18 Collision Free Scheduling for X m …. 2 1 Collision vector for X 1 : collision 0 : no collision

Anshul Kumar, CSE IITD slide 19 Collision Free Scheduling for Y 1 0 m….2 1 Collision vector for Y 1 : collision 0 : no collision

Anshul Kumar, CSE IITD slide 20 Latency Cycles from State Diagram Latency Cycles (1, 8) (1, 8, 6, 8) (3) (6) (3, 8) (3, 6, 3) Simple Latency Cycles (no figure repeats) (1, 8) (3) (6) (3, 8) (6, 8) Greedy Latency Cycles (1, 8) (3) - from different starting states

Anshul Kumar, CSE IITD slide 21 Minimum Average Latency (MAL) MAL > max no. of check marks in any row MAL < avg latency of any greedy cycle avg latency of any greedy cycle < no. of 1’s in initial collision vector + 1

Anshul Kumar, CSE IITD slide 22 Upper Bound on MAL Consider a greedy cycle (k 1,k 2,..,k n ) Let p = no. of 1’s in initial collision vector  k 1 < p + 1 k 2 < 2 p - k k 3 < 3 p - k 1 - k …. k n < n p - k 1 - k 2 … - k n-1 + n  k 1 + k 2 … + k n < n p + n  MAL < p + 1