1. CSL718 : Superscalar Processors
Renaming and Reordering
30th Jan, 2006
Anshul Kumar, CSE IITD

2. Why Renaming and Reordering?
Register Renaming
Removes false dependencies (WAR and WAW)
Reordering Buffer (ROB)
Ensures sequential consistency of interrupts (precise vs imprecise interrupts)
Facilitates speculative execution
Anshul Kumar, CSE IITD

3. RAW, WAR and WAW (in Static Pipeline)IF D RF EX WB
RAW IF D RF EX WB IF D RF EX WB
WAR IF D RF EX WB IF D RF EX EX EX WB
WAW IF D RF EX WB
Anshul Kumar, CSE IITD

4. RAW, WAR and WAW (in Superscalar)
write IF IS DP EX WB
RAW
read IF IS DP EX WB
WAW
WAR
write IF IS DP EX WB
Anshul Kumar, CSE IITD

5. Implementation using scoreboard bit
write IF IS DP EX WB
RAW
read IF IS DP EX WB
WAW
WAR
write IF IS DP EX WB
b  0
Anshul Kumar, CSE IITD

6. CDC 6600 like Implementation
b  0
b  1
write IF IS DP EX WB
RAW
read IF IS
WAW DP EX WB
WAR
write IF IS DP EX WB
b  0
Anshul Kumar, CSE IITD

7. IBM 360 like Implementation
write IF IS DP EX WB
RAW
read IF IS
WAW DP EX WB
WAR
write IF IS DP EX WB
b  0
Anshul Kumar, CSE IITD

8. Use of Renaming write read write IF IS DP EX WB RAW IF IS DP EX WB WAW
WAR
write IF IS DP EX WB
Anshul Kumar, CSE IITD

9. Register renaming write R5 RAW read R5 WAR write R5 RAW read R5
Anshul Kumar, CSE IITD

10. Who does renaming? Compiler Hardware Done statically
Limited by registers visible to compiler
Hardware
Done dynamically
Limited by registers available to hardware
Anshul Kumar, CSE IITD

11. Types of renaming buffers
Separate renaming register file and architectural register file
Combined renaming and architectural register file
Renaming combined with reordering
Renaming combined with shelving and reordering
Anshul Kumar, CSE IITD

12. How renaming works? (in context of combined reg file)
register address
from instruction
mapping
physical register file
(larger than architectural
register file)
Anshul Kumar, CSE IITD

13. Types of mapping Indexed Associative Inexpensive Two steps required
Look up index
Read value
Associative
Expensive
Single step associative access
Anshul Kumar, CSE IITD

14. Renaming with indexed access
entry index
valid
value value
valid
register
number
mapping table
physical register file
Anshul Kumar, CSE IITD

15. Renaming with associative access
match
register
number
entry reg
valid num
value value latest
valid
physical register file (associative)
Anshul Kumar, CSE IITD

16. Handling interrupts these can “commit” status of instruction execution
at the time of
interrupt
completed
under execution
not started
program
order
Anshul Kumar, CSE IITD

17. Speculative execution
predicted
branch
speculative
execution
don’t commit till correctness
of prediction is determined
Anshul Kumar, CSE IITD

18. instructions commit/retire
Reordering
instruction enter i i x x
i: issued
x: in execution
f: finished x f x f
instructions commit/retire
Anshul Kumar, CSE IITD

19. Using ROB with RF Register to reservation stations/FUs File from FUs
Anshul Kumar, CSE IITD

20. Future file and history file
Register
File
ROB
use in case of interrupts
from FUs
Future
File
to reservation stations/FUs
update in case of interrupts
displaced values
History
File
Future
File
to reservation stations/FUs
from FUs
Anshul Kumar, CSE IITD

21. Combining renaming and reordering
Use physical register file as ROB as well
Maintain status about committed and uncommitted values
Anshul Kumar, CSE IITD

22. How much to speculate? Handle exceptions in speculated instructions?
handle only low cost exception events such as first level cache miss
wait if expensive exceptional event occurs such as second level cache miss or TLB miss
Speculating through multiple branches
needed when branches are frequent or clustered
even handling multiple branches in a cycle may be required
Anshul Kumar, CSE IITD