Quality Driven SystemC Design By Nasir Mahmood

Hybrid Approach The idea here is to combine the strengths of simulation – namely the ability to handle large designs and ease of use – with the strengths of formal verification – namely, its thoroughness

Verification Environment SystemC provides an integrated environment for design simulation and verification It could provide automatic verification methodologies using automated reasoning using formal methods It can utilize Matlab and Simulink framework for accelerate testbench generation and analysis It enable functional verification at different levels of abstraction

Design- and verification gap

Approach To cope with the increasing design sizes the level of abstraction in the design of electronic systems has been raised over the last years The system engineer writes a C or C++ model of the system to check the concepts and algorithms at the system level.

System Design Flow

SystemC Design Flow

Enhanced Design and Verification Flow

Main advantages : new Verification Flow System design and verification flow covering all levels of abstraction Dedicated verification techniques at each level of abstraction System-level verification by improved constraint-based simulation Block-level verification based on improved property checking Top-level verification with checkers and formal hardware/software co-verification Integration of debugging approaches to identify contradictions in specified tests High verification quality due to automatic coverage checks Usage of code coverage techniques to ensure system-level and top- level verification quality Formal coverage analysis for property checking to guarantee verification quality at the block level

My Approach Use of library of already verified block level modules Use integrated approach for verification at different levels of abstraction A SystemC based automated Environment for Verification of Virtual Prototype Communication Systems

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