PLC Counter Instructions 9 PLC Counter Instructions

Objectives Use count up instructions to create PLC ladder logic diagrams. Use count down instructions to create PLC ladder logic diagrams. Reset counter instructions. Connect different counter instructions and cascade counter instructions. Use timer and counter instructions to create PLC ladder logic diagrams. © Goodheart-Willcox Co., Inc.

PLC Counter Instructions Double-input counter Single-input counter © Goodheart-Willcox Co., Inc.

PLC Counter Instructions (Cont.) Similar to the timer instruction. Displayed in block format or coil format. Single-input in block format. Allen-Bradley SLC 500 series programmable logic controller uses one input. Addresses can be C5:0 to C5:255. Can have up to 256 instructions. © Goodheart-Willcox Co., Inc.

PLC Counter Instructions (Cont.) Count up: Accumulated register value increments (counts up) whenever the counter input device changes state. Count down: Accumulated register value decrements (counts down) whenever the counter input device changes state. © Goodheart-Willcox Co., Inc.

PLC Counter Instruction Registers Preset register (C5:0.PRE): Used to hold the preset counter number. Accumulated register (C5:0.ACC): Holds the accumulated counter number. Status register: Holds flag bits that are used by the PLC to keep track of the operation of counter C5:0. © Goodheart-Willcox Co., Inc.

PLC Counter Instruction Registers (Cont.) Two flag bits: Count bit. Done bit C5:0/DN. © Goodheart-Willcox Co., Inc.

PLC Counter Instruction Registers (Cont.) Overflow bit (OV). Underflow bit (UN). Update accumulator bit (UA): Used with high-speed counter (HSC) instructions. © Goodheart-Willcox Co., Inc.

SLC 500 Counter Instruction Registers and Status Bits © Goodheart-Willcox Co., Inc.

PLC Count Up Instructions Accumulated register increments when counter input device changes state. © Goodheart-Willcox Co., Inc.

PLC Ladder Logic Diagram Using Count Up Instruction © Goodheart-Willcox Co., Inc.

PLC Count Down Instructions Accumulated register decrements whenever the counter input device changes state. Preset value for the count down usually is a negative number. Content of the accumulated register decrements from its initial value of zero to the negative preset number. © Goodheart-Willcox Co., Inc.

Count Down Instruction Connected to a NO Input © Goodheart-Willcox Co., Inc.

PLC Count Instructions Comparison Count down instruction: Done bit (C5:0/DN) resets to zero. Done coil de-energizes when the content of the accumulated register decrements to the preset number. Count up instruction: Done bit (C5:0/DN) is enabled. Done coil energizes when the content of the accumulated register is equal to the content of the preset register. © Goodheart-Willcox Co., Inc.

Connecting PLC Counter Instructions In some manufacturing operations: Content of an entire section of a conveyor needs to be known at one time. Place two proximity sensors on the conveyor. One sensor connected to count up instruction. One sensor connected to count down instruction. © Goodheart-Willcox Co., Inc.

Connecting PLC Counter Instructions (Cont.) Conveyor and proximity sensors and how counting is accomplished. © Goodheart-Willcox Co., Inc.

Connecting PLC Counter Instructions (Cont.) Infeed proximity switch: Connected to the count up instruction. Outfeed proximity switch: Connected to the count down instruction. © Goodheart-Willcox Co., Inc.

Cascading Counters In some industrial applications: Counters are cascaded so that one counter increments or decrements when another counter is done. Used mainly in material handling and process control environments. © Goodheart-Willcox Co., Inc.

PLC Ladder Logic Diagram Using Cascading Counters © Goodheart-Willcox Co., Inc.

PLC Ladder Logic Diagram with Counters and Timers © Goodheart-Willcox Co., Inc.

Glossary Count bit: Bit that is enabled every time the counter counts up for count up instructions or down for count down instructions. Count down: Instruction where the accumulated register decrements whenever there is a change in the counter input. Count up: Instruction where the accumulated register increments whenever there is a change in the counter input. © Goodheart-Willcox Co., Inc.

Glossary Double-input counter: Counter that uses one input to enable the counter and another input to count the number of pulse signals. Overflow bit (OV): Bit that turns on when the positive number in a count up instruction increments to +32,767 decimal. Single-input counter: Counter that has one input to enable and count the signals. © Goodheart-Willcox Co., Inc.

Glossary Underflow bit (UN): Bit that turns on when the negative number in a count down instruction decrements to –32,768 decimal. © Goodheart-Willcox Co., Inc.