EDA Standards – The SPIRIT View Gary Delp VP and Technical Director SPIRIT

2 © LSI EDA Standards Listing – not complete – shown to provide a scope to the problem IEEEIEEE-SA – LSI Corporate membership –P1685: IP-XACT: XML Meta data and Tool Interfaces –P1734: QIP – IP Quality Metrics –P1735: IP Encryption –P1801: Low Power Design Intent Accellera P1801 Open SystemC Initiative (OSCI) –SystemC –TLM (Transaction Level Modeling Silicon Integration Initiative (Si2) –Design Technology Council (DTC) –Low Power Coalition (LPC) –Open Access Coalition (OAC) The SPIRIT Consortium –IP-XACT –SystemRDL – register description language –Debug, verification, Documentation working groups –Interworking with: OASIS, Eclipse, Si2, Low Power Virtual Socket Interconnect Alliance (VSIA) – finished! –Transferred to IEEE, The SPIRT Consortium, OCP, and the Public Domain

2007 SoC Conference - Bill Chown3 Contributing Members Board of Directors Associate Members March 2008 Membership

2007 SoC Conference - Bill Chown4 Reviewing Members Now More Than 100 Members Strong Future Wireless Technologies

2007 SoC Conference - Bill Chown5 Scope – Charter – 3-9 Members Informal discussion Study Group Formation Work Group Formation Requirements document PSS Contributions Work Group Meetings Validation Criteria Validation Donation To IEEE Contributing Requirements Proof of concept Document & Example Creation Alpha Distribution Beta Distribution Public Distribution Development Process of The SPIRIT Consortium

2007 SoC Conference - Bill Chown6  IP-XACT is The SPIRIT Consortium specification for describing IP  Enables automated design creation and configuration  Enables designers to include specialist knowledge in their components  Benefits  Build repeatable design flows  Access to machine readable description of all aspects of IP using the IP-XACT XML databook  Common interface descriptions  Tool independent Design Environment Meta Data (XML) Generators IP Views IP Library for IP Descriptions specifies …

The IP ECO System IP design IP Qualification IP Evaluation IP Verification IP Integration Chip-level Design and verification Chip Manufacture IP packaging Process Technology IP verification Industry Bodies Can Aid the Effective Eco-System Connectivity T VSI ^ ^ ^ ^ ^ IP Tag Insert T VSI T VSI T VSI T VSI T VSI T VSI T VSI T VSI IP Tag Check T VSI    IP Tag Merge

8 © LSI The Low Power Standards “Program” (you can’t tell the players without “The Program”) Cadence Power Forward Initiative Common Power Format SI 2 Low Power Coalition Accellera Unified Power Format IEEE NESCOM & DASC CPF Study Group P1801 Working Group IEEE 1801 Standard This slide is included to group the acronyms so that the format comparison can be understood in context Common Power Format

9 © LSI Verification “Standards” In the past, System Verilog and SystemC had many separate implementations, not interoperable. OVM –Cadence & Mentor combined their contributions and just released VMM –Synopsys VMM “donated” to Accellera IP-XACT descriptions work for both Performance is an issue when there are generic interfaces Why we care – verification across the corp. is unifying and sharing Action: Participate in Accellera and IEEE to provide guidance to the vendors