Electrical Engineering 348: ELECTRONIC CIRCUITS I Dr. John Choma, Jr. Professor of Electrical Engineering University of Southern California Department of Electrical Engineering– Electrophysics University Park; Mail Code: 0271 Los Angeles, California [Office] [Fax] [Cell] Spring Semester 2001

EE 348 – Spring 2001J. Choma, Jr.Slide 2 EE 348: Lecture Supplement Notes SN1 Review of Basic Circuit Theory and Introduction To Fundamental Electronic System Concepts 01 January 2001

EE 348 – Spring 2001J. Choma, Jr.Slide 3 Outline Of Lecture Thévenin’s & Norton’s Theorems Basic Electronic System Concepts Steady State Sinusoidal Response Transient Response

EE 348 – Spring 2001J. Choma, Jr.Slide 4 Thevénin’s Theorem Concept  Two Terminals Of Any Linear Network Can Be Replaced By Voltage Source In Series With An Impedance  Thévenin Voltage Is “Open Circuit” Voltage At Terminals Of Interest  Thévenin Impedance Is Output Impedance At Terminals Of Interest Linear Load  Thévenin Concept Applies To Linear Or Nonlinear Load  Voltage V L Is Zero If No Independent Sources Are Embedded In The Load

EE 348 – Spring 2001J. Choma, Jr.Slide 5 Thévenin Model Parameters Thévenin Voltage  Zero Load Current  V oc  V th Thévenin Impedance  “Ohmmeter” Calculation   Thévenin Voltage Is Set To Zero By Nulling All Independent Sources In Linear Network Superposition

EE 348 – Spring 2001J. Choma, Jr.Slide 6 Thévenin Example Bipolar Emitter Follower Equivalent Circuit Load Is The Capacitor, C l Calculate:  Thévenin Voltage Seen By Load  Thévenin Impedance Seen By Load  Transfer Function, V o (s)/V s (s)  3–dB Bandwidth

EE 348 – Spring 2001J. Choma, Jr.Slide 7 Thévenin Voltage And Impedance Thévenin Voltage Gain Thévenin Impedance

EE 348 – Spring 2001J. Choma, Jr.Slide 8 Thévenin Output Model Gain Resistance

EE 348 – Spring 2001J. Choma, Jr.Slide 9 Transfer Function (Gain) Gain At Zero Frequency Is A th Bandwidth Definition 3–dB Bandwidth (Radians/Sec)

EE 348 – Spring 2001J. Choma, Jr.Slide 10 Frequency and Phase Responses –45°

EE 348 – Spring 2001J. Choma, Jr.Slide 11 Input Impedance Very Large Zero Frequency Input Impedance Other Characteristics  Left Half Plane Pole And Left Half Plane Zero  Non-Zero High Frequency Impedance

EE 348 – Spring 2001J. Choma, Jr.Slide 12 Voltage Delivery To Load System Problem  Voltage Generated By Some Linear Network Is To Be Supplied To A Fixed Load Impedance, Z l  Because The Source Network Is Linear, Its Output Can Be Represented By A Thévenin Circuit (V s — Z s )  Assume Thévenin Source and Load Impedances are Fixed Load Voltage  If |Z l | << |Z s |, Much Of The Source Voltage Is “Lost” In The Source Impedance  If |Z l | = |Z s |, 50% Of The Source Voltage Is Lost, Resulting In A factor Of Two Attenuation Or 6 dB Gain Loss.  Many Systems Are Intolerant Of Such A Loss

EE 348 – Spring 2001J. Choma, Jr.Slide 13 Insertion Of Voltage Buffer

EE 348 – Spring 2001J. Choma, Jr.Slide 14 Impact Of Voltage Buffer Practical Buffer  Z out Very Small  Z in Very Large  A buf Near Unity Effect Of Ideal Buffer

EE 348 – Spring 2001J. Choma, Jr.Slide 15 Norton’s Theorem Concept  Two Terminals Of Any Linear Network Can Be Replaced By A Current Source In Shunt With An Impedance  Norton Current Is “Short Circuit” Current At Terminals Of Interest  Norton Impedance Is Output Impedance At Terminals Of Interest And Is Identical To Thévenin Output Impedance Linear Load  Norton Concept Applies To Linear Or Nonlinear Load  Voltage V L Is Zero If No Independent Sources Are Embedded In The Load

EE 348 – Spring 2001J. Choma, Jr.Slide 16 Norton Model Parameters Norton Current  Zero Load Voltage  I sc  I no Norton Impedance  “Ohmmeter” Calculation   Norton Current Is Set To Zero By Nulling All Independent Sources In Linear Network Superposition

EE 348 – Spring 2001J. Choma, Jr.Slide 17 Thévenin–Norton Relationship From Thévenin Model: From Norton Model: Thévenin–Norton Equivalence:

EE 348 – Spring 2001J. Choma, Jr.Slide 18 Current and Voltage Sources Ideal Voltage Source Ideal Current Source

EE 348 – Spring 2001J. Choma, Jr.Slide 19 Voltage Amplifier Ideal Properties  Infinitely Large Input Impedance, Z in  Zero Output Impedance, Z out  Sufficiently Large Voltage Gain, A v, Independent Of Input Voltage, V I and Output Voltage V o Circuit Schematic Symbol

EE 348 – Spring 2001J. Choma, Jr.Slide 20 Transconductor Ideal Properties  Infinitely Large Input Impedance, Z in  Infinitely Large Output Impedance, Z out  Sufficiently Large Transconductance, G m, Independent Of Input Voltage, V I and Output Voltage V o Circuit Schematic Symbol

EE 348 – Spring 2001J. Choma, Jr.Slide 21 Current Amplifier Ideal Properties  Zero Input Impedance, Z in  Infinitely Large Output Impedance, Z out  Sufficiently Large Current Gain, A i, Independent Of Input Voltage, V I and Output Voltage V o Circuit Schematic Symbol

EE 348 – Spring 2001J. Choma, Jr.Slide 22 Transresistance Amplifier Ideal Properties  Zero Input Impedance, Z in  Zero Output Impedance, Z out  Sufficiently Large transresistance, R m, Independent Of Input Voltage, V I and Output Voltage V o Circuit Schematic Symbol

EE 348 – Spring 2001J. Choma, Jr.Slide 23 Max Voltage & Current Transfer Voltage Transfer Current Transfer  M aximum Voltage Transfer Requires Very Small Z th  Maximum Current Transfer Requires Very Large Z th

EE 348 – Spring 2001J. Choma, Jr.Slide 24 Power Dissipated In The Load Sinusoidal Steady State Load Power

EE 348 – Spring 2001J. Choma, Jr.Slide 25 Maximum Power Transfer Condition: Max Power:

EE 348 – Spring 2001J. Choma, Jr.Slide 26 Example–50  Transmission Line Parameters  Antenna RMS Voltage Signal Is 10  V  Transmission Line Coupling To RF Stage Behaves Electrically As A 50 Ohm Resistance Power To RF Input Port  Maximized When RF Input Impedance Is 50 Ohms  dBm Value:

EE 348 – Spring 2001J. Choma, Jr.Slide 27 Second Order Lowpass Filter Lowpass Filter  Unity Gain Structure (Gain At Zero Frequency Is One)  Ideal Transconductors KVL (Solve For V o /V s )

EE 348 – Spring 2001J. Choma, Jr.Slide 28 Filter Transfer Function Generalization: Parameters  DC Gain = H(0) = 1  Undamped Resonant Frequency =  o = (g m1 g m2 /C 1 C 2 ) 1/2  Damping Factor =  = (g m2 C 1 / 4g m1 C 2 ) 1/2

EE 348 – Spring 2001J. Choma, Jr.Slide 29 Lowpass 2 nd Order Function Poles At s = –p 1 & s = –p 2 Undamped Frequency: Damping Factor:  P 1 & P 2 Real Results In  >1 (Overdamping) Or  = 1 (Critical Damping)  P 1 & P 2 Complex Requires P 1 & P 2 Conjugate Pairs, Whence  < 1 (Underdamping)

EE 348 – Spring 2001J. Choma, Jr.Slide 30 Lowpass – Critical Damping Critical Damping   = 1  p 1 = p 2 Frequency Response  Bandwidth Constraint  Bandwidth | H(0)| |H(j  )| in dB -3 dB B  Slope = –40 db/dec

EE 348 – Spring 2001J. Choma, Jr.Slide 31 Lowpass – Overdamping Overdamping   > 1  p 1 < p 2  Poles Are Real Numbers  Dominant Pole System Implies p 1 << p 2 Dominant Pole Bandwidth  Transfer Function Approximation  Bandwidth Approximation  Gain-Bandwidth Product

EE 348 – Spring 2001J. Choma, Jr.Slide 32 Lowpass Frequency Response 3-dB Down

EE 348 – Spring 2001J. Choma, Jr.Slide 33 Lowpass Phase Response

EE 348 – Spring 2001J. Choma, Jr.Slide 34 Lowpass Step Response Input Is Unit Step [X(s) = 1/s] Overdamped (  > 1) Critical Damping (  = 1   o = p 1 = p 2 )

EE 348 – Spring 2001J. Choma, Jr.Slide 35 Real Pole Step Response Plots 95% Line

EE 348 – Spring 2001J. Choma, Jr.Slide 36 Lowpass – Underdamping Overdamping   < 1  p 1 = p 2 * =  o e j  Circuit Bandwidth  Proportional To  o  Equal To  o For  = Frequency Response Peaking  |H(j  )| Not Monotone Decreasing Frequency Function If  <  Non-Zero Frequency Associated With Maximal |H(j  )|

EE 348 – Spring 2001J. Choma, Jr.Slide 37 Underdamped Frequency Response 3-dB Line

EE 348 – Spring 2001J. Choma, Jr.Slide 38 Underdamped Phase Response

EE 348 – Spring 2001J. Choma, Jr.Slide 39 Delay Response Steady State Sinusoidal Response If Phase Angle Is Linear With Frequency  Constant Time Shift, Independent Of Signal Frequency  No Phase Angle Is Ever Perfectly Linear Over Entire Passband Envelope Delay

EE 348 – Spring 2001J. Choma, Jr.Slide 40 Underdamped Delay Response

EE 348 – Spring 2001J. Choma, Jr.Slide 41 Underdamped Step Analysis Input Is Unit Step [X(s) = 1/s] Underdamped (  < 1) Characteristics  Damped Oscillations  Oscillation For Zero Damping (  = 0)  Undamped Frequency Is Oscillatory Frequency For Zero Damping

EE 348 – Spring 2001J. Choma, Jr.Slide 42 Underdamped Step Response