指導教授：劉致為 博士 學生：魏潔瑩 台灣大學電子工程學研究所 The Characteristics and Simulations of Si/SiGe Heterojunction at Strained-Si Devices 指導教授：劉致為 博士 學生：魏潔瑩 台灣大學電子工程學研究所

Outline Introduction Introduction to Si-based Heterostructure Device Fabrication Simulation and Result Discussion Conclusion

Technology Scaling Question: How much more scaling is left? New technology generation introduced every 3 or 2 years. (0.18um, 0.13um, 90nm,.… ) Scaling improves cost and performance-- leading to new applications and growth. Question: How much more scaling is left?

Smaller FET Needs Thinner Gate Oxides The conduction channel must be controlled by the gate, not by The drain. As L is reduced, drain-to-channel capacitance increases. Therefore, gate-to-channel capacitance must also be raised, i.e., oxide must be thinner. 1975: 100nm, 2003: 1.2nm. How much thinner can it get? L Gate Oxide Source Drain Cg Cd Ref [1]

12Å Gate Oxide -- 3 SiO2 molecules thick Ref [1]

High-k Dielectrics Reduce Gate Leakage 1.5 2.0 2.5 Effect Oxide Thickness (nm) Jg reduction > 6 orders SiO2 High-k Dielectric 1.E+00 High-k Dielectric 1.E-02 Gate Jg (A/cm2) 1.E-04 1.E-06 1.E-08 1.0 Ref [1]

I  mobility x charge = mobility x ( V-Vt ) / Tox In order to reduce power use, V is reduced and Vt and Tox are kept large. Unfortunately, I drops. Large I is needed to keep circuit speed high. What is needed : high mobility material

Outline Introduction Introduction to Si-based Heterostructure Device Fabrication Simulation and Result Discussion Conclusion

Lattice Structure and Heterostructures Ref [2]

Strained Silicon Transistor Tensile strain can increase silicon electron holes mobilities. Need strained silicon film with low defect density at low cost. Strained Si Si 1 - x Ge Graded SiGe Region Si Substrate Relaxed SiGe 20nm Ref [1]

The Effect of Strain on Si Conduction Band Ref [2]

Band Alignment between Si and Si0.7Ge0.3 1% Ge = 6meV for CB and VB Ref [3]

Effective Mobility of Strained-Si 65% enhancement at 1.0 MV/cm μ= eτ/ m* τ= scattering time constant m*=effective mass Ref [4]

Outline Introduction Introduction to Si-based Heterostructure Device Fabrication Simulation and Result Discussion Conclusion

The Structure of the surface-channel Strained-Si n-MOSFET 0.8 μm design rule 100 mm-wafer line ~1 μm graded SiGe buffer layer ~1 μm uniform relaxed Si0.8Ge0.2 12-24nm strained layer thickness are grown by UHV/CVD 20 nm LTO as gate oxide Dit = 1E11 cm-2eV-1 Ref [5]

Outline Introduction Introduction to Si-based Heterostructure Device Fabrication Simulation and Result Discussion Conclusion

Parameters χSS = 4.05 + 0.6x Eg,SS = 1.12 - 0.4x εr, SS = 11.8 χSiGe = 4.05 Eg,SiGe = 1.12 - 0.4x εr, SiGe = 11.8 + 4.2x x : Ge content, χ: affinity, Eg : bandgap energy, SS : strained-Si Simulator: ISE TCAD 8.5 DESSIS

Structure and Band Diagram of Strained-Si/SiGe/Si MOS Capacitor

Simulated Band Diagrams for Different Gate Biases

Measured and Simulated Quasi Static C-V Characteristics

Measured NMOS Capacitor C-V with Different Strained-Si Thickness

Simulated NMOS Capacitor C-V with Different Strained-Si Thickness

Simulated NMOS Capacitor C-V as A Function of Ge Content

Simulated Energy Band Diagram for Different Ge Content in PMOS Capacitor

Hole Density Ratio in Strained-Si

Asymmetric Strain

Simulated Current Enhancement in Asymmetric Strain

Outline Introduction Introduction to Si-based Heterostructure Device Fabrication Simulation and Result Discussion Conclusion

Conclusion Due to Fermi level pinning effect, the C-V characteristics in NMOS capacitor exhibits a more obvious plateau than in PMOS capacitor. Less Ge content and larger strained layer thickness must be chosen to sustain enough great inversion hole density ratios in strained-Si pMOSFET.

Since more strain and thinner strained layer are taken to keep mobility enhancement, the compromise must be made. Modeling of hole confinement on the C-V characteristics in strained-Si must be investigated.

Reference [1] Chenming Hu, IEDMS 2002 presentation. [2] Kern Rim, Ph. D. dissertation 1999. [3] J. J. Welser, Ph. D. dissertation 1994. [4] M. H. Lee et al., “Comprehensive Low-Freguency and RF Noise Characteristics in Strained-Si NMOSFETs”, IEDM 2003. [5] C. C. Lee et al., ”The effects of mobility and saturation velocity on deep submicron strained Si NMOSFETs,” IDEMS, 2002.