1 of 14 1/15 Synthesis-driven Derivation of Process Graphs from Functional Blocks for Time-Triggered Embedded Systems Master thesis Student: Ghennadii Sivatki Supervisor and examiner: Paul Pop

2 of 14 2/15 Outline  Embedded systems  Automotive electronics  Embedded systems design flow  Functional analysis: EAST-ADL  Platform selection, Mapping, Scheduling  Case study in Generic modeling environment (GME)  Preliminaries  System architecture  Time-triggered embedded systems  Software architecture  Application model  Functional blocks  Process graphs

3 of 14 3/15 Outline, cont.  Functional blocks to process graphs  Problem formulation  Motivation  Cost function: schedulable? Schedule length.  Related Work  Translation strategies  Straightforward translations  Tabu-search based optimization  Translation heuristic  Integration with EAST-ADL/GME  Experimental results  Comparison of translation strategies  Case study

4 of 14 4/15 Embedded Systems General purpose systemsEmbedded systems Microprocessor market shares in 1999

5 of 14 5/15 Embedded Systems Characteristics  Dedicated functionality (not general purpose computers)  Embedded into a host system  Complex architectures  Embedded systems design constraints  Correct functionality  Performance, timing constraints: real-time systems  Development cost, unit cost, size, power, flexibility, time-to- prototype, time-to-market, maintainability, correctness, safety, etc.  Difficult to design, analyze and implement  System-level design  Reuse and flexibility

6 of 14 6/15 Automotive Electronics  What is “automotive electronics”?  Vehicle functions implemented with electronics  Body electronics  System electronics (chassis, engine)  Information/entertainment

7 of 14 7/15 Distributed Architecture

8 of 14 8/15 Wiring: Point-to-Point vs. Network Weight5 Kg Kg Length of insulated wire50 m1500 m Number of connectors35300 Number of terminals Number of individual wires  1994: Wiring same price as the engine!  Solution  Replace point-to-point wiring with a multiplexing network  Protocols  LIN: Local Interconnect Network (body electronics)  CAN: Controller Area Network (system electronics)  TTP: Time Triggered Protocol (system electronics)  MOST: Media Oriented Systems Transport (infotainment)

9 of 14 9/15... I/O Interface Comm. controller CPU RAM ROM ASIC System Architecture: Network of Clusters  Hardware archtiecture  Software architecture

10 of 14 10/15 Typical Application: Controller

11 of 14 11/15 Body Electronics: Dashboard Controller  Constraints  Wheel signal: 0-1,000 Hz  Engine speed: Hz  Architectures  Motorola 68HC05  Needs external drivers  Motorola 68HC11  On-chip drivers Microcontrollers

12 of 14 12/15 Body Electronics  Constrains  Very low cost  ms (reaction of the human operator)  Characteristics  Node  Single-chip 8 bit micro-controller  > 100 bytes of RAM  > 1K of ROM  I/O points to connect sensors and actuators  Simple network interface  Network  Low bandwidth, ten to twenty nodes (LIN)

13 of 14 13/15 System Electronics: Engine Controller  Function  Improve engine performance  Reduce fuel consumption  =air/fuel ratio  Constraints  Engine speed: 6000 RPM  recomputed every 20 ms; control algorithm: 5 ms!  Architecture  Motorola 68332

14 of 14 14/15 System Electronics  Constraints  Low cost  Typical control loop periods range from 1 ms to 20 ms  Characteristics  Node  Architecture influenced by its real-time constraints:  8, 16, 32 bit microprocessors, up to 16K of RAM and 256K of ROM  Memory grows more than 25% / year  Complex network interface  I/O points to connect sensors and actuators  Network  High bandwidth, CAN or TTP

15 of 14 15/15 Embedded Systems Design  TODO:  Insert here slides about  Embedded systems design flow  Functional analysis: EAST-ADL  Platform selection, Mapping, Scheduling  Case study in Generic modeling environment (GME)

16 of 14 16/15 Event-Driven vs. Time-Driven Systems  Event-driven systems  Activation of processes is done at the occurrence of significant events  Scheduling event-triggered activities  Fixed-priority preemptive scheduling  Response time analysis: calculate worst-case response times for each process  Schedulability test: response times smaller than the deadlines  Time-driven systems  Activation of processes is done at predefined points in time  Scheduling time-triggered activities  Static cyclic non-preemptive scheduling  Building a schedule table: static cyclic scheduling (e.g., list scheduling)

17 of 14 17/15 I/O Interface TTP Controller CPU RAM ROM ASIC Node Time-Triggered Embedded Systems  Hard real-time distributed systems.  Nodes interconnected by a broadcast communication channel.  Nodes consisting of: TTP controller, CPU, RAM, ROM, I/O interface.  Communication between nodes is based on the time-triggered protocol.

18 of 14 18/15 Time Triggered Protocol H. Kopetz, Technical University of Vienna. Intended for distributed real-time control applications that require high degree of dependability and predictability. Recommended by the X-by-Wire Consortium for use in safety critical applications in vehicles. Integrates all the services required in the design of fault-tolerant distributed real-time systems. S0S0 S1S1 S2S2 S3S3 S0S0 S1S1 S2S2 S3S3 TDMA Round Cycle of two rounds Slot Bus access scheme: time-division multiple-access (TDMA). Schedule table located in each TTP controller: message descriptor list (MEDL). I/O Interface TTP Controller CPU RAM ROM ASIC Node

19 of 14 19/15 Software Architecture

20 of 14 20/15 Application Modeling: Functional Blocks  Assumptions (the functional blocks are pre-processed)  One single period  Loops are removed  Links represent synchronous communication  Worst-case execution time (WCET) is given for each elementary function f1 f3 f2f4 f5

21 of 14 21/15 P4P4 P4P4 P5P5 P5P5 P7P7 P7P7 P 13 P 15 First processor Second processor ASIC P0P0 P 18 P1P1 P1P1 P2P2 P2P2 P3P3 P3P3 P6P6 P6P6 P8P8 P8P8 P9P9 P9P9 P 10 P 11 P 12 P 14 P 16 P 17 Application Modeling: Process Graphs

22 of 14 22/15 Problem Formulation  Input  System architecture  Application modeled as functional blocks  A synthesis algorithm (mapping and scheduling) S1S1 S0S0 P1P1 P4P4 P2P2 m1m1 m2m2 m3m3 m4m4 P3P3 N1N1 N2N2 Bus P1P1 P4P4 P2P2 P3P3 N1N1 N2N2 Mapping Where to place a process? Scheduling How to execute processes?

23 of 14 23/15 Problem Formulation, cont.  Output  A process graph such that the implementation (obtained using the given synthesis algorithm) is schedulable  The synthesis algorithm produces  Mapping  Schedule tables

24 of 14 24/15 Motivational Example #1 f1 f1/2 f1/1

25 of 14 25/15 Motivational Example #1, cont. N2N2 a) P1P1 N1N1 N2N2 b) P 1/1 N1N1 P 1/2

26 of 14 26/15 Motivational Example #2 f1 f2 f4 f3f5 f6 f4/1f4/2

27 of 14 27/15 Motivational Example #2 Deadline for P 6 : D 6 P4P4 P5P5 P3P3 N2N2 N3N3 P6P6 Met a) P2P2 P1P1 P2P2 P3P3 P4P4 N1N1 N2N2 XX X X X P5P5 X Deadline for P 5 : D 5 P3P3 P6P6 P5P5 P4P4 P2P2 P1P1 P1P1 N1N1 P 4/2 P5P5 P3P3 N2N2 N3N3 P6P6 Met b) P2P2 P1P1 N1N1 P 4/1 N2N2 N3N3 N1N1 TTP N3N3 P6P6 70 X X X X X40X Missed Met

28 of 14 28/15 Optimization Strategy

29 of 14 29/15 Experimental Results

30 of 14 30/15 Experimental Results, Cont.  Case study in GME  Vehicle cruise controller