Status of the CSC Track-Finder Darin Acosta University of Florida

CMS Week, 25 Feb 2003D.Acosta, University of Florida2 CSC Muon Trigger Scheme CSC CFEB ALCT 1 of 24 CFEB 1 of 2 LVDB 1 of 5 Anode Front-end Board Cathode Front-end Board Anode LCT Board MPCMPC DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB CCBCCB CONTROLLERCONTROLLER Peripheral Crate on iron disk (1 of 48) Trigger Timing & Control CSC Track-Finder Crate (1) Trigger Motherboard (9) DAQ Motherboard (9) Clock Control Board Optical link In underground counting room On detector Muon Portcard (1) EMU part: mostly in productionTriDAS part: Second generation prototypes Trigger Primitives 3-D Track-Finding and Measurement Sector Processor (12) Muon Sorter (1)

CMS Week, 25 Feb 2003D.Acosta, University of Florida3 1 st Prototype Track-Finder Tests (2000) Sector Processor (Florida) Sector Receiver (UCLA) Clock Control Board (Rice) Bit3 VME Interface CustomChannelLinkBackplane(Florida) Muon Port Card (Rice) Very successful, but overall CSC latency was too high -- New 2002 design improves latency Results included in Trigger L1 TDR

CMS Week, 25 Feb 2003D.Acosta, University of Florida4 CSC Track-Finder Crate CSC Track-Finder Crate SR / SP SR / SP SR / SP SR / SP SR / SP SR / SP SR / SP SR / SP SR / SP SR / SP SR / SP SR / SP CCB SBS 620 Controller Sector Processor Clock and Control Board Muon Sorter From MPC (chamber 4) From MPC (chamber 3) From MPC (chamber 2) From MPC (chamber 1B) From MPC (chamber 1A) To DAQ MS Single Track-Finder Crate Design with 1.6 Gbit/s optical links Second generation prototypes 4 merged boards

CMS Week, 25 Feb 2003D.Acosta, University of Florida5 Combined SR/SP 2002 Prototype è Problems encountered attempting layout using in-house tools è Sent to industry for completion of layout using Cadence Allegro è Final board takes 16 layers è Cost of manufacture, assembly, and parts is about $20K / board

CMS Week, 25 Feb 2003D.Acosta, University of Florida6 SP2002 Main Board (SR Logic) 3 SRs Optical Transceivers 15 x 1.6 Gbit/s Links Front FPGA TLK2501 Transceiver Phi Local LUT Eta Global LUT Phi Global LUT EEPROM VME/ CCB FPGA DC-DC Converter

CMS Week, 25 Feb 2003D.Acosta, University of Florida7 SP Trigger Logic From SP2000 to SP2002 mezzanine card Xilinx Virtex-2 XC2V4000 ~800 user I/O (Mezzanine card also used for CSC sorter)

CMS Week, 25 Feb 2003D.Acosta, University of Florida8 Tests underway…

CMS Week, 25 Feb 2003D.Acosta, University of Florida9 Optical Link Test Results Using pseudo-random test built into TLK2501 chipset è SP02 optical loopback test over 1 m optical cable p No errors! è SP02 optical loopback test over 100 m cable p BER = 10  12 è MPC  SP02 optical test over 100 m cable p BER = 3×10  13 Controlled MPC  SP02 chain test è Download 255 bx of data for one MPC (3 muons × 32 bits), preceding each iteration with a L1 Reset è Send data over three 100 m cables into SP, and readout p Counting the 0’s transmitted between iterations, 30 link errors observed in total from 3 links over 16 hours (3×10 14 bits)  BER = 10  13 Thus, about 1 error / hour, likely from clock jitter

CMS Week, 25 Feb 2003D.Acosta, University of Florida10 Optical Link Tests (Cont’d) Controlled MPC  SP02 chain test without L1 Reset è This is how we would like to operate è Explicitly check data sent vs. data received è Tests underway, code still needs improvements (e.g. to issue L1 Reset if link fails and does not recover)

CMS Week, 25 Feb 2003D.Acosta, University of Florida11 Schedule Proposed schedule as of Feb-2003: è Feb.’03: SP02 prototype completed, initial tests begin è Mar.’03: MPC  SP optical link tests è Apr.’03: SP memory and trigger logic tests è May.’03: CSC system tests with cosmic rays and beam tests at CERN è June ’03… : Tests with Muon Sorter and DT Track-Finder √ √ (April)

CMS Week, 25 Feb 2003D.Acosta, University of Florida12 Test Beam Plans Plan to test CSC Trigger all the way to the Track- Finder in May/June beam tests è Complete chain test from 2 detectors to peripheral crate electronics to Track-Finder crate electronics! Structured beam period: 23 May  1 June è Two DAQ systems will run concurrently: CSC DAQ and Track-Finder DAQ è Track-Finder will just log inputs, not generate a track trigger è Goal is to validate trigger primitives are found efficiently on correct bx and successfully received over optical links è Record as much data as possible under various detector configurations for future track identification studies Asynchronous beam period: 13 June  1 July è Possibility to test a unified DAQ using “slice test” software developed in XDAQ

CMS Week, 25 Feb 2003D.Acosta, University of Florida13 Conclusions Second generation CSC Track-Finder prototype completed Optical link tests between Port Card and Sector Receiver successful è Measurable (but small ~ ) bit error rate seen Plan to take T-F to beam test later this month Tests of SR memories and SP trigger logic to follow Interface tests with CSC Sorter and DT T-F also planned