ECE 331 – Digital System Design Constraints in Logic Circuit Design (Lecture #13) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6 th Edition, by Roth and Kinney, and were used with permission from Cengage Learning.

Fall 2010ECE Digital System Design2 Material to be covered … Supplemental Chapter 8: Sections 1 – 5

Fall 2010ECE Digital System Design3 Logic Circuits Thus far, we have focused on the design of logic circuits in terms of their logical behavior only. When designing a logic circuit, we must also consider several real-world constraints, including:  Noise  Fan-out  Fan-in  Power consumption  Time delay  Transient behavior

Fall 2010ECE Digital System Design4 Logic Circuits To do so, we must first understand how the logic levels are represented.

Fall 2010ECE Digital System Design5 Logic Gates Logic gates are the fundamental building blocks of combinational (and sequential) logic circuits. They are an abstraction.

Fall 2010ECE Digital System Design6 Logic Gates Logic gates are, in fact, electrical circuits.

Fall 2010ECE Digital System Design7 Logic Gates As such, the logic levels must be represented using an electrical characteristic. Most technologies use voltages to represent the logic levels.  TTL  CMOS Some, but very few, technologies use currents to represent the logic levels.

Fall 2010ECE Digital System Design8 Representing Logic Levels Ideally, a single voltage value is specified for each logic level.  VDD (power) → Logic 1  GND (ground) → Logic 0 Logic 1 = high voltage Logic 0 = low voltage

Fall 2010ECE Digital System Design9 Representing Logic Levels In reality, a range of voltages is specified for each logic level. GND VDD V 1,MIN V 0,MAX Logic 1 Logic 0 Undefined Threshold voltages

Fall 2010ECE Digital System Design10 Representing Logic Levels Furthermore, voltage ranges, for logic 1 and logic 0, are specified for both the input and the output of a logic gate. They are defined in terms of four parameters  V OH = output high voltageV IH = input high voltage  V OL = output low voltageV IL = input low voltage These are specified in the data sheet for the corresponding logic gate. They differ from one logic family to another.

Fall 2010ECE Digital System Design11 Representing Logic Levels InputOutput GND VDD V IH V IL Logic 1 Logic 0 Undefined GND VDD V OH V OL Logic 1 Logic 0 Undefined V IH = min. volt. for Logic 1 V IL = max. volt. for Logic 0 V OH = min. volt. for Logic 1 V OL = max. volt. for Logic 0

Fall 2010ECE Digital System Design12 Example: 74LS08 V IH, V IL V OH, V OL

Fall 2010ECE Digital System Design13 Example: 74LS32 V IH, V IL V OH, V OL

Fall 2010ECE Digital System Design14 Example: 74HC32 V IH, V IL V OH, V OL

Fall 2010ECE Digital System Design15 Noise

Fall 2010ECE Digital System Design16 Noise External noise sources can cause the logic gate output voltages to deviate from their expected values. V OH V OL V IH V IL noise As a result, the voltages may be misinterpretted.  An output low voltage not interpreted as a logic 0  An output high voltage not interpreted as a logic 1

Fall 2010ECE Digital System Design17 Noise Margin Must select logic gates to allow the logic circuit to function properly even in the presence of noise. The noise margin is the amount of noise that the logic circuit can withstand while still functioning properly. It is a measure of the noise immunity provided by the logic circuit. The noise margin is defined for both logic 1 and logic 0  NM H = V OH – V IH High noise margin  NM L = V IL – V OL Low noise margin

Fall 2010ECE Digital System Design18 Noise Margin GND VDD V IH V IL Logic 1 Logic 0 Undef GND VDD V OH V OL Logic 1 Logic 0 Undef GND VDD V OH V OL V IH V IL NM H NM L Noise Margin

Fall 2010ECE Digital System Design19 Noise Margin The noise margin must be positive, for both logic 1 and logic 0, for the circuit to function properly.  V OH (driver) > V IH (load)  V OL (driver) < V IL (load) A negative noise margin implies that the voltage output by the driving gate will not be interpreted properly by the load gate(s). DriverLoad V OH V OL V OH + noise V OL + noise

Fall 2010ECE Digital System Design20 Example: Noise Margin Calculate NM H and NM L when a 74LS08 drives a 74LS32.

Fall 2010ECE Digital System Design21 Example: Noise Margin Calculate NM H and NM L when a 74LS08 drives a 74HC32.

Fall 2010ECE Digital System Design22 Example: Noise Margin Calculate NM H and NM L when a 74HC32 drives a 74LS08.

Fall 2010ECE Digital System Design23 Example: Noise Margin Show table of calculations

Fall 2010ECE Digital System Design24 Fan-out

Fall 2010ECE Digital System Design25 Fan-out To the input of n logic gates Fan-out is the number of logic gate inputs that can be properly driven by a single logic gate output.

Fall 2010ECE Digital System Design26 Fan-out Logic gates can sink and source a limited amount of current, both at the input and the output. These currents are defined in terms of four parameters  I OH = output high currentI IH = input high current  I OL = output low currentI IL = input low current These are specified in the data sheet for the corresponding logic gate. They differ from one logic family to another.

Fall 2010ECE Digital System Design27 Fan-out Fan-out is limited by the output current of the driving gate and the input current of the load gates. Fan-out is calculated, simply, as the ratio of the output current (of the driving gate) to the total input current (of the load gates). It must be calculated for both the logic 1 output (high- state) and the logic 0 output (low-state). Both must be considered when designing a logic circuit.  Select the worst-case as the limit.

Fall 2010ECE Digital System Design28 Fan-out Low-state Fan-out = Floor[ I OL_max (driver) / I IL_max (load) ] High-state Fan-out = Floor[ I OH_max (driver) / I IH_max (load) ]

Fall 2010ECE Digital System Design29 Example: Fan-out Calculate the fan-out when a 74LS08 drives one or more 74LS32.

Fall 2010ECE Digital System Design30 Example: Fan-out Calculate the fan-out when a 74LS08 drives one or more 74HC32.

Fall 2010ECE Digital System Design31 Example: Fan-out Calculate the fan-out when a 74HC32 drives one or more 74LS08.

Fall 2010ECE Digital System Design32 Example: Fan-out Show table of calculations

Fall 2010ECE Digital System Design33 Fan-out Exceeding fan-out limit leads to  Increase in output-low voltage (V OL ) And possibly the wrong logic state  Decrease in output-high voltage (V OH ) And possibly the wrong logic state  Increase in temperature And possible destruction of the circuit / device  Increase in propagation delay

Fall 2010ECE Digital System Design34 forn =1V f forn =4V f V DD Gnd Time0 (c) Propagation times for different values ofn Effect of Fan-out on Gate Delay

Fall 2010ECE Digital System Design35 Electrical Constraints Devices in the same logic family have the same electrical characteristics. Devices in different logic families often have different electrical characteristics. In order to interconnect devices of different logic families:  Must consider the noise margin voltage constraint  Must consider the fan-out current constraint

Fall 2010ECE Digital System Design36 Fan-in

Fall 2010ECE Digital System Design37 Fan-in Fan-in is the number of inputs to a logic gate. It is limited by  Silicon area  Input capacitance Thus, when designing a logic circuit, we must consider the practical limit on the fan-in of the logic gates.

Fall 2010ECE Digital System Design38 Fan-in As we have already seen,  A SOP expression is most easily realized using a two-level AND-OR circuit  A POS expression is most easily realized using a two-level OR-AND circuit However, if the logic circuit requires logic gates that exceed the fan-in limit, an alternate design will be necessary.  Manipulate the Boolean expression  Realize using a multiple-level circuit

Fall Example: Fan-in Given the following logic function, design a combinational logic circuit using 3-input NOR gates only. f(a, b, c, d) = Ʃ m(0, 3, 4, 5, 8, 9, 10, 14, 15) First, find the minimum sum-of-products for f ′.

Fall 2010ECE Digital System Design40 Example: Fan-in Then factor the expression for f ′ to reduce the maximum number of gate inputs to three. Finally complement f ' to get f. f ′ = b′d(a′c′ + ac) + a′c(b + d′) + abc′ f = [b + d′ + (a + c)(a′ + c′)][a + c′ + b′d][a′ + b′ + c]

Fall 2010ECE Digital System Design41 Questions?