M. Dahlström, Z. Griffith, M. Urteaga, M.J.W. Rodwell University of California, Santa Barbara, CA, USA X.-M. Fang, D. Lubyshev, Y. Wu, J.M. Fastenau and W.K. Liu IQE Inc, Betlehem, PA, USA , fax InGaAs / InP DHBT’s with > 370 GHz f  and f max using a Graded Carbon-doped Base

ParameterInP/InGaAsSi/SiGebenefit (simplified) collector electron velocity3E7 cm/s1E7 cm/slower  c, higher J base electron diffusivity40 cm 2 /s~2-4 cm 2 /slower  b base sheet resistivity 500 Ohm5000 Ohmlower R bb comparable breakdown fields Consequences, if comparable scaling & parasitic reduction: ~3:1 higher bandwidth at a given scaling generation ~3:1 higher breakdown at a given bandwidth Problem for InP: SiGe has much better scaling & parasitic reduction Present efforts in InP research community Development of low-parasitic, highly-scaled, high-yield fabrication processes Why mesa DHBT? Continue to advance the epitaxial material for improved speed Motivation for InP HBTs

High speed HBT: some standard figures of merit Small signal current gain cut-off frequency (from H 21 )… Maximum power gain (from U)… Collector capacitance charging time when switching…

How do we make HBT’s faster… key device parameterrequired change collector depletion layer thicknessdecrease 2:1 base thicknessdecrease 0.707:1 emitter junction widthdecrease 4:1 collector junction widthdecrease 4:1 emitter resistance per unit emitter areadecrease 4:1 current densityincrease 4:1 base contact resistivity (if contacts lie above collector junction) decrease 4:1 base contact resistivity (if contacts do not lie above collector junction) unchanged Required transistor design changes required to double transistor bandwidth …easily derived from geometry / resistivity / velocity relationships (C ’s,  ’s, C/I ’s all reduced 2:1)

How do we improve gate delay for digital IC’s ?

Scaling Laws, Collector Current Density, C cb charging time Collector Field Collapse (Kirk Effect) Collector Depletion Layer Collapse Collector capacitance charging time is reduced by thinning the collector while increasing current

Challenges with Scaling Collector-base scaling Mesa HBT: collector under base Ohmics. Base Ohmics must be one transfer length → sets minimum size for collector Solution: reduce base contact resistivity → narrower base contacts allowed Unavailable solution: decouple base & collector dimensions Compromise: physically undercut the collector semiconductor Emitter Ohmic Resistivity: must improve in proportion to square of speed improvements Current Density: self-heating, current-induced dopant migration, dark-line defect formation Loss of breakdown avalanche V br never less than collector bandgap (1.12 V for Si, 1.4 V for InP) ….sufficient for logic, insufficient for power Yield !! submicron InP processes have progressively decreasing yield

Fast DHBTs: high current density  high temperature Max T rise in Collector Thermal conductivity of InGaAs ~ 5 W/mK Thermal conductivity of InP ~ 68 W/mK Average Tj (Base-Emitter) =26.20°C Measured Tj=26°C—good agreement Conclusion… Minimize InGaAs thickness in subcollector Caused by Low K of InGaAs Prof. Ian Harrison

InGaAs 3E19 Si 400 Å InP 3E19 Si 800 Å InP 8E17 Si 100 Å InP 3E17 Si 300 Å InGaAs 8E19  5E19 C 300 Å Setback 3E16 Si 200 Å InP 3E18 Si 30 Å InP 3E16 Si 1030 Å SI-InP substrate Grade 3E16 Si 240 Å InP 1.5E19 Si 500 Å InGaAs 2E19 Si 125 Å InP 3E19 Si 3000 Å Compared to previous UCSB mesa HBT results: Thinner InP collector—decrease  c Collector doping increased—increase J Kirk Thinner InGaAs in subcollector—remove heat Thicker InP subcollector—decrease R c,sheet High f  DHBT Layer Structure and Band Diagram V be = 0.75 V, V ce = 1.3 V Emitter Collector Base

UCSB mesa HBT process flow

InP HBT limits to yield: non-planar process Emitter contact Etch to base Liftoff base metal Failure modes Yield quickly degrades as emitters are scaled to submicron dimensions Emitter planarization, interconnects

SEM of device before polymide passivation Profile of high frequency device… um wide emitter by optical lithography 1.0 um thick -- emitters as small as 0.4 um wide fabricated -- self aligned base contact as small as 0.3 um on both sides of emitter Front view… Emitter contact width = 0.6 um, base mesa width = 1.2 um Physical emitter width = 0.5 um, collector undercut = 0.2 um Area collector / Area emitter = 1.0 / 0.5 = 2

Device dimensions device area = 4.2  m 2 emitter metal 0.7 x 8 mm emitter junction 0.6 x 7 mm base mesa width = 1.7  m DC gain: 8-10 n c /n b : 1.04/1.55 V br,CEO : 5 V J c = 8 mA/  m V ce =2.5 V J max = 12 mA/  m V ce =1.5 V Device results—DC and Gummel plots for 150 nm collector

Device results—DC and rf… 30 nm InGaAs base: 8*10 19 /cm 3 → 5*10 19 /cm nm InP collector 0.6 x 7  m emitter 0.5  m base contacts base sheet: 603  /square base contacts: 20  -  m 2 emitter contacts:  -  m 2 collector sheet: 12  /square collector contacts: 9  -  m 2

S-parameters and delay terms Smith chart Summary of delay terms S 21 /20 S 12 x5 S 11 S 22 Extraction :  ex =10 Ω-  m 2 v c =4.5  10 5 m/s Device dimensions device area = 4.2  m 2 emitter metal 0.7 x 8  m emitter junction 0.6 x 7  m base mesa width = 1.7  m

Base metal resistance for very narrow contacts Resistance of e-beam deposited metals higher than “book” values. Metal resistivity increases when t base metal <1000 A …An important contributor to R bb for the base contact (Pd/Ti/Pd/Au, 25/170/170/630)  s,base metal = 0.5 Ω/sq  3-8 Ω added to R bb for 0.3  m base contact width this will generate thermal instability if R ex is very low—(how low…?)

Base-collector capacitance variation with J e C cb /I c  0.26 ps / V

Rf performance over time, under bias time = 3 minutes, f  and f max  308 GHz time = 3 hours, f  and f max  308 GHz DC bias conditions: V cb = 0.35 V, V ce  1.3 V J = 8.5 mA/  m 2

UCSB static frequency divider designs w/ DRC 2003 model Divider speed w/ base mesa width 2.1 um1.7 um1.3 um R ex = 15  m 2 R bb = 25  m R bb = R bb = R bb = R ex = 10R bb = R bb = R bb = R bb =  m 530  m UCSB/ONR: Z. Griffith

Conclusions… We have achieved record performance for f  in a InP mesa DHBT—370GHz, along with maintaining simultaneously high f max —375GHz Much of the gains attributed to the work on the process and the collector — physical undercut thinning active material—2000A to 1500A doping higher to push J kirk,max higher thinning InGaAs subcollector contact—500A to 125A, remove heat What are we concentrating on now in our mesa process… Contact resistance: need to drop R ex for simultaneous increase in ft and fmax Find way to increase base metal thickness: high ft and without lowing fmax Alternative base grade scheme—dual grade doping and alloy Acknowledgment— This work is supported by the Office of Naval Research under contract N

On wafer LRL calibration… LRL calibration using on wafer Open, Zero-length through line, and delay line OSLT used to check U in DC-50 GHz band Probe pads separated by 460  m to reduce p-p coupling RF environment not ideal, need: thinning, air bridges, vias for parasitic mode suppression S-parameter measurement test structure

SEM of patterned passivation w/ interconnects Patterned polyimide passivation plasma etch Coplanar waveguide interconnects