1. 50-200 GHz InP HBT Integrated Circuits for Optical Fiber and mm-Wave Communications Mark Rodwell University of California, Santa Barbara rodwell@ece.ucsb.edu 805-893-3244, 805-893-3262 fax 2002 ECOC Conference, September, Copenhagen

2. Applications: optical fiber transceivers at 40 Gb/s and higher Key advantages for: TIA, LIA, Modulator driver Losing competition with SiGe: MUX/CMU, DMUX/CDR excessive power problems with integration scale 80 & 160 Gb may come in time world may not need capacity for some time WDM might be better use of fiber bandwidth This presentation: how InP HBT ICs will be able to do 160 Gb/s "If you build it, they will come." (today, this argument is not convincing).

3. mmWave Transmission UCSB Atmospheric attenuation is LOW (~4 dB/km) at bands of interest 60-80 GHz, 120-160 GHz, 220-300 GHz (Weather permitting) Geometric path losses are LOW due to short wavelengths. 4 mW transmitter power sufficient for 10 Gb/s transmission over 500 meters range given 20 cm diameter antennas

4. How Do We Improve the Bandwidth of Bipolar Transistors ? Thinner base, thinner collector  higher f , but higher R bb C cb, R ex C cb … what parameters are really important in HBTs ? how do we improve HBT performance ?

5. HBT scaling: layer thicknesses reduce T b by  2:1   b improved 2:1 reduce T c by 2:1   c improved 2:1 note that Ccb has been doubled..we had wanted it 2:1 smaller 2:1 improved device speed: keep G's, R's, I's, V's constant, reduce 2:1 all C's,  's Rodwell

6. HBT scaling: lithographic dimensions Ccb/Area has been doubled..we had wanted it 2:1 smaller …must make area=L e W e 4:1 smaller  must make  W e & W c 4:1 smaller Base Resistance R bb must remain constant  L e must remain ~ constant reduce collector width 4:1 reduce emitter width 4:1 keep emitter length constant 2:1 improved device speed: keep G's, R's, I's, V's constant, reduce 2:1 all C's,  's Rodwell

7. HBT scaling: emitter resistivity, current density Emitter Resistance R ex must remain constant but emitter area=L e W e is 4:1 smaller resistance per unit area must be 4:1 smaller increase current density 4:1 reduce emitter resistivity 4:1 2:1 improved device speed: keep G's, R's, I's, V's constant, reduce 2:1 all C's,  's Collector current must remain constant but emitter area=L e W e is 4:1 smaller and collector area=L c W c is 4:1 smaller current density must be 4:1 larger Rodwell

8. Scaling Laws for fast HBTs Rodwell, IEEE Trans. Electron Devices, Nov. 2001

9. Optical Transmitters / Receivers are Mixed-Signal ICs TIA: small-signal LIA: often limiting MUX/CMU & DMUX/CDR: mostly digital Small-signal cutoff frequencies (f , f max ) are ~ predictive of analog speed Limiting and digital speed much more strongly determined by (I/C) ratios InP HBT has been well-optimized for f  & f max, less well for digital speed

10. How do we improve logic speed ?

11. Technology Roadmaps for 40 / 80 / 160 Gb/s

12. Challenges with Scaling: Collector-base scaling Mesa HBT: collector under base contacts. Base contacts have nonzero resistivity → sets minimum contact size Solution: reduce base contact resistivity Solution: decouple base & collector dimensions e.g. buried SiO 2 in junction (SiGe), undercut-mesa (InP) Emitter Ohmic Resistivity: must improve in proportion to square of speed improvements Current Density: increases rapidly device heating, current-induced dopant migration, dark-line defect formation SiGe at 5*10 5 A/cm 2, InP at 1*10 5 Loss of breakdown voltage InP superior to SiGe at equal speed Yield InP HBT processes must reach yield sufficient for DMUX/CMU progressively more difficult at submicron dimensions

13. Low C cb InP HBT structures undercut-collector transferred-substrate Allows deep submicron collector scaling high mm-wave gains low yield at deep submicron scaling mm-wave device, not mixed-signal Pursued by several research groups Also has uncertain yield at submicron geometries The conservative III-V device structure Yet, I assert that even this device is not viable of mass manufacturing if > 3000 transistors per IC are sought Need improved device structures for high yield at 0.1  m scaling Narrow-mesa with ~1E20 carbon-doped base

14. Transferred-Substrate HBTs UCSB ONR

15. 140-220 GHz network analysis HP8510C network analyzer & Oleson Microwave Lab frequency Extenders GGB waveguide-coupled probes 75-100 GHz network analysis GGB waveguide-coupled probes HP W-band test set 1-50 GHz network analysis GGB coax-connectorized probes HP 0.045-50 GHz test set 220 GHz On-Wafer Network Analysis Miguel Urteaga Accurate measurements are not easy HBT Ccb is very small (~5 fF) → S 12 easily masked by probe-probe coupling increase probe separation: reference plane extensions On-wafer LRL calibration standards ultra-thin microstrip for reduced mode coupling

16. Emitter: 0.3 x 18  m 2, Collector: 0.7 x 18.6  m 2 I c = 5 mA, V ce = 1.1 V Submicron InAlAs/InGaAs HBTs: Unbounded (?!?) Unilateral power gain 45-170 GHz unbounded U UCSB ONR emitter collector Miguel Urteaga Urteaga, Int. Journal High Speed Electronics and Systems, to be published gain resonances likely due to IMPATT effects Rodwell, Int. Symp. Compound Semiconductors, Tokyo, Oct. 2001

17. 175 GHz Single-Stage Amplifier UCSB Miguel Urteaga 6.3 dB gain at 175 GHz

18. Deep Submicron Bipolar Transistors for 140-220 GHz Amplification Miguel Urteaga 1-transistor amplifier: 6.3dB @ 175 GHz 3-transistor amplifier: 8 dB @ 195 GHz raw 0.3  m transistor: 6-11 dB power gain @ 200 GHz UCSB

19. Sangmin Lee f max = 462 GHz, f t = 139 GHz InGaAs/InP DHBT, 3000 Å InP collector 0.5  m x 8  m emitter (mask) 0.4  m x 7.5  m emitter (junction) 1.0  m x 8.75  m collector BV CEO = 8 V at J E =5*10 4 A/cm 2

20. High Current, High Breakdown Voltage InP DHBT 8-finger device 8 x ( 1  m x 16  m emitter ) 8 x ( 2  m x 20  m collector )

21. W band 128  m 2 power amplifier UCSB common base PA 0.5mm x 0.4 mm, A E =128  m 2 ARO MURI f 0 =85 GHz, BW 3dB =28 GHz,G T =8.5 dB, P 1dB =14.5 dBm, P sat= 16dBm Bias: I c =78 mA, V ce =3.6 V

22. High Speed Amplifiers 18 dB, DC--50+ GHz UCSB Dino Mensa PK Sundararajan 8.2 dB, DC-80 GHz >397 GHz gain x bandwidth from 2 HBTs S 22 S 11 S 21

23. Ultra Wideband Mesa InP/InGaAs/InP DHBTs Mattias Dahlstrom (UCSB) Amy Liu (IQE) 2000 Å InP collector 300 Å InGaAs base 8E19 to 5E19 graded C base doping InAlAs/InGaAs base-collector grade. 500 Ohm/square base sheet resistance < 2*10 -7 Ohm-cm 2 base contact resistance 7.5 V Breakdown 282 GHz f  >450 GHz f max, operation to 500 kA/cm 2 at 1.7 volts UCSB / IQE

24. 87 GHz HBT master-slave latch InAlAs /InGaAs/InP MESA DHBT 400 Å base, 2000 Å collector, 9 V BVCEO 200 GHz ft, 180 GHz fmax 2.5 x 10 5 A/cm 2 operation PK Sundararajan, Zach Griffith UCSB 200 GHz logic program

25. 8 GHz  ADC Technology 0.7 um InAlAs /InGaAs/InP MESA DHBT 400 Å base, 2000 Å collector, 9 V BVCEO, 200 GHz ft, 180 GHz fmax 2.5 x 10 5 A/cm 2 operation Design simple 2nd-order g m -C topology comparator is 87 GHz MSS latch integration by capacitive loads 3-stage comparator, RTZ gated DAC Results 133 dB (1 Hz) SNR at 74 MHz equivalent to ~8.8 bits at 200 MS/s UCSB PK Sundararajan, Zach Griffith 200 GHz logic program 975 kHz FFT bin size 8 GHz clock rate 65.5 MHz signal 64:1 oversampling ratio

26. InP vs. Si/SiGe HBTs: recent experience at 40 Gb/s 40 Gb/s IC development during internet bubble 7 of my ex-Ph.D. students involved, at 4 different companies personally actively involved as consultant InP HBT technology 1  m design-rule processes easily developed, good reliability, yield ok for 2000 HBTs (not more), 170 GHz f , f max, 7 volt V br, 3 mA (min) device, 60 GHz clock Resulting ICs TIA, LIA, 6 V differential modulator driver: quite successful MUX/CMU, DMUX/CDR: limited to 4:1 (yield, power) SiGe necessary for 16:1 standards-compliant MUX & DMUX market is presently very small InP requires lower NRE than SiGe InP critically needs: higher integration scales, scaling for speed & power

27. High current density 10 mA/  m 2 T-shaped polysilicon emitter 0.25  m junction wide contact low resistance, high yield Thin intrinsic base: low  b Thick extrinsic base: low R bb Low C cb collector junction collector pedestal CVD/CMP SiO 2 planarization regrown poly extrinsic base High-yield, planar processing high levels of integration LSI and VLSI capabilities SiGe clock rates up to 65 GHz Much more complex ICs than feasible in InP HBT InP HBT must reach higher integration scales or will cease to compete Very strong features of SiGe-bipolar transistors

28. InP vs. Si/SiGe HBTs: materials vs. scaling advantages Advantages of InP ~20:1 lower base sheet resistance, ~5:1 higher base electron diffusivity ~3:1 higher collector electron velocity, ~4:1 higher breakdown-at same f . Disadvantage of InP: archaic mesa fabrication process Presently only scaled to ~ 1 um (production) large emitters, poor emitter contact: low current density: 2 mA/um 2 high collector capacitance nonplanar device - low yield low integration scales

29. InP HBT limits to yield: non-planar process Emitter contact Etch to base Liftoff base metal Failure modes Yield degrades as emitters are scaled to submicron dimensions Emitter planarization, interconnects

30. MBE growth of Polycrystalline n+ InAs Polycrystalline InAs grown on SiN: Doping = 1.3  10 19 cm -3, Mobility = 620 cm 2 /Vs Results in doping-mobility product of 8  10 21 (V s cm) -1 InGaAs lattice matched to InP: Doping = 1.0  10 19 cm -3, Mobility = 2200 cm 2 /Vs Results in doping-mobility product of 22  10 21 (V s cm) -1 Polycrystalline InAs has potential as an extrinsic emitter contact. Dennis Scott SiGe HBT process: extensive use of non-selective-area poly-Si regrowth Can a similar technology be developed for InP ?

31. Process Flow: Single-poly- regrowth InP HBT

32. Regrown-Poly-InAs-Emitter HBT Dennis Scott

33. Submicron Scaling of InP HBTs InP HBTs are a mixed-signal, not a MIMIC technology for MIMICs, sub-0.1-  m InP HEMTs are hard to beat mixed-signal is fiber ICs, ADCs, DACs, digital frequency synthesis these are 1000 -- 40,000 transistor ICs InP HBTs are struggling to compete with SiGe HBT application demands transistor counts near/beyond yield limits large emitter junctions→ high current → power near acceptable limits no decisive speed advantage in relevant circuits: digital logic materials advantages being squandered by inadequate scaling InP HBTs can be scaled to operate at 160 Gb/s key is scaling emitter to 0.2  m, collector to 0.4  m contact resistivities challenging but feasible; yield is key concern Critically needed for InP HBTs highly scaled process: 0.2  m emitters, 0.4  m collectors highly planar and high-yield fabrication processes small emitter junctions (0.2  m x 0.5  m) for acceptable power

34. In Case of Questions

35. What HBT parameters determine logic speed ? Caveats: assumes a specific UCSB InP HBT (0.7 um emitter, 1.2 um collector 2kÅ thick, 400 Å base, 1.5E5 A/cm^2) ignores interconnect capacitance and delay, which is very significant Yoram Betser, Raja Pullela

36. Submicron HBTs have very low C cb (< 5 fF) HBT S12 is very small Standard 12-term VNA calibrations do not correct S12 background error due to probe-to-probe coupling Solution Embed transistors in sufficient length of transmission line to reduce coupling Place calibration reference planes at transistor terminals Line-Reflect-Line Calibration Standards easily realized on-wafer Does not require accurate characterization of reflect standards Characteristics of Line Standards are well controlled in transferred-substrate microstrip wiring environment Accurate Transistor Measurements Are Not Easy Transistor in Embedded in LRL Test Structure 230  m Corrupted 75-110 GHz measurements due to excessive probe-to-probe coupling

37. Can we trust the calibration ? S11 of through About –40 dB 140-220 GHz calibration looks OK75-110 GHz calibration looks Great S11 of open About 0.1 dB / 3 o error dB S21 of through line is off by less than 0.05 dB S11 of open S11 of short S11 of through Probe-Probe coupling is better than –45 dB Miguel Urteaga

38. Negative Unilateral Power Gain ??? YES, if denominator is negative This may occur for device with a negative output conductance (G 22 ) or some positive feedback (G 12 ) Select G L such that denominator is zero: Can U be Negative? What Does Negative U Mean? Device with negative U will have infinite Unilateral Power Gain with the addition of a proper source or load impedance AFTER Unilateralization Network would have negative output resistance Can support one-port oscillation Can provide infinite two-port power gain Simple Hybrid-  HBT model will NOT show negative U

39. Scaling Laws, Collector Current Density, C cb charging time Collector Field Collapse (Kirk Effect) Collector Depletion Layer Collapse Collector capacitance charging time is reduced by thinning the collector while increasing current Rodwell

40. Why isn't base+collector transit time so important ?

41. HBT distributed amplifier UCSB PK Sundararajan 11 dB, DC-87 GHz AFOSR TWA with internal ft-doubler cells