ELEC 5270 – Low Power Design of Electronic Circuits Spring 2009 Grant Lewis 1

 3-bit Counter has 14 transitions in 8 cycles  14/8 = 1.75 transitions per cycle  N-bit Counter has 2(2 N -1) transitions  Transitions per cycle → 2 as N→ ∞ 4-bit transitions/clock 5-bit bit bit bit bit

 A =  B =  C =  8 logic gates Synthesize in Leonardo Spectrum 3

 3-bit counter has 8 transitions in 8 cycles  8/8 = 1 transition per cycle  N-bit counter has 2 N transitions  Transitions per cycle is 1 for any size counter  For large counters, ratio of transitions for Decimal to Gray →

 Gray Encoding can be accomplished by  Binary to Gray conversion  Directly Synthesizing Gray Counter  Binary to Gray conversion is accomplished with 2 XOR gates 5

 With optimizations, adds one logic gate (total 9 logic gates) 6

 A =  B =  C =  Adds 4 logic gates (total 12 gates) 7

 Power analysis conducted with powersim.18 μm, 1.8V supply 8 Decimal Encoding Decimal to Gray % Reduction Gray Encoding % Reduction # of Gates %12-50% # of Glitches % % Glitch Power (μW) % % Dynamic Power (μW) % % Leakage Power (μW) % % Logic Power (μW) % % Total Power (μW) % %

 Much of dynamic power consumption comes from glitches  Can be reduced by path balancing  Directly implementing gray counter in logic removes ~1/2 of the glitches, however consumes more leakage and logic power due to increase in number of logic gates  Overall, gray counters are more power efficient 9

 Hakenes, R.; Manoli Y. “A Segmented Gray Code for Low-Power Microcontroller Address Buses”. EUROMICRO Conference, Proceedings. 25 th, Pages 240 – 243, Vol. 1  Doran, R. W. “The Gray Code”. Centre for Discrete Mathematics and Theoretical Computer Science, March,  Mehta, Huzefa et al. “Some Issues in Gray Code Addressing”. Proceedings of the 6th Great Lakes Symposium on VLSI, Pages 178 –