Semiconductor Memories Mohammad Sharifkhani

Outline Introduction Non-volatile memories

Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory EPROM E 2 PROM FLASH Random Access Non-Random Access SRAM DRAM Mask-Programmed Programmable (PROM) FIFO Shift Register CAM LIFO

Memory Timing: Definitions

Memory Architecture: Decoders Word 0 Word 1 Word 2 WordN 2 2 N 2 1 Storage cell M bitsM N words S 0 S 1 S 2 S N - 2 A 0 A 1 A K - 1 K = log 2 N S N - 1 Word 0 Word 1 Word 2 WordN 2 2 N 2 1 Storage cell S 0 Input-Output (M bits) Intuitive architecture for N x M memory Too many select signals: N words == N select signals K = log 2 N Decoder reduces the number of select signals Input-Output (M bits) Decoder

Array-Structured Memory Architecture Problem: ASPECT RATIO or HEIGHT >> WIDTH Amplify swing to rail-to-rail amplitude Selects appropriate word

Hierarchical Memory Architecture Advantages: 1. Shorter wires within blocks 2. Block address activates only 1 block => power savings

Block Diagram of 4 Mbit SRAM Subglobal row decoder Global row decoder Subglobal row decoder Block 30 Block K Array Block 0 Block 1 Local row decoder [Hirose90]

Contents-Addressable Memory Address Decoder I/O Buffers Commands 2 9 Validity Bits Priority Encoder Address Decoder I/O Buffers Commands 2 9 Validity Bits Priority Encoder

Memory Timing: Approaches DRAM Timing Multiplexed Adressing SRAM Timing Self-timed

Introduction Non volatile memories

Non-Volatile Memories The Floating-gate transistor (FAMOS) Floating gate Source Substrate Gate Drain n + n +_ p t ox t Device cross-section Schematic symbol G S D

Floating-Gate Transistor Programming 0 V - 5 V 0 V DS Removing programming voltage leaves charge trapped 5 V V 5 V DS Programming results in higherV T. 20 V 10 V5 V 20 V DS Avalanche injection

A “Programmable-Threshold” Transistor

FLOTOX EEPROM Floating gate Source Substrate p Gate Drain n 1 n 1 FLOTOX transistor Fowler-Nordheim I-V characteristic 20–30 nm 10 nm -10 V 10 V I V GD

EEPROM Cell WL BL V DD Absolute threshold control is hard Unprogrammed transistor might be depletion  always on  2 transistor cell

Flash EEPROM Control gate erasure p-substrate Floating gate Thin tunneling oxide n 1 source n 1 drain programming Many other options …

Cross-sections of NVM cells EPROMFlash Courtesy Intel

Basic Operations in a NOR Flash Memory― Erase

Basic Operations in a NOR Flash Memory― Write

Basic Operations in a NOR Flash Memory― Read

NAND Flash Memory Unit Cell Word line(poly) BL Courtesy Toshiba Select line Source line (Diff. Layer)

NAND Flash Memory Word linesSelect transistor Bit line contactSource line contact Active area STI Courtesy Toshiba

Characteristics of State-of-the-art NVM

Outline Introduction Non-volatile memories RAM

Read-Write Memories (RAM)  STATIC (SRAM)  DYNAMIC (DRAM) Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended

6-transistor CMOS SRAM Cell WL BL V DD M 5 M 6 M 4 M 1 M 2 M 3 BL Q Q

CMOS SRAM Analysis (Read) WL BL V DD M 5 M 6 M 4 M 1 V V V BL Q = 1 Q = 0 C bit C

CMOS SRAM Analysis (Read) Voltage rise [V] Cell Ratio (CR) 2.53 Voltage Rise (V)

CMOS SRAM Analysis (Write) BL = 1 = 0 Q = 0 Q = 1 M 1 M 4 M 5 M 6 V DD V WL

CMOS SRAM Analysis (Write)

6T-SRAM — Layout V DD GND Q Q WL BL M1 M3 M4M2 M5M6

Decreasing Word Line Delay

Resistance-load SRAM Cell Static power dissipation -- Want R L large Bit lines precharged to V DD to address t p problem M 3 R L R L V DD WL QQ M 1 M 2 M 4 BL

SRAM Characteristics

Introduction Non-volatile memories RAM –SRAM –DRAM

3-Transistor DRAM Cell No constraints on device ratios Reads are non-destructive Value stored at node X when writing a “1” = V WWL -V Tn WWL BL1 M 1 X M 3 M 2 C S 2 RWL V DD V 2 V T D V V 2 V T BL2 1 X RWL WWL

3T-DRAM — Layout BL2BL1GND RWL WWL M3 M2 M1

1-Transistor DRAM Cell Write: C S is charged or discharged by asserting WL and BL. Read: Charge redistribution takes places between bit line and storage capacitance Voltage swing is small; typically around 250 mV.  V BL V PRE –V BIT V PRE – C S C S C BL == V

DRAM Cell Observations  1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out.  DRAM memory cells are single ended in contrast to SRAM cells.  The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation.  Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design.  When writing a “1” into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than V DD

Sense Amp Operation D V(1) V V(0) t V PRE V BL Sense amp activated Word line activated

1-T DRAM Cell Uses Polysilicon-Diffusion Capacitance Expensive in Area M 1 word line Diffused bit line Polysilicon gate Polysilicon plate Capacitor Cross-section Layout Metal word line Poly SiO 2 Field Oxide n + n + Inversion layer induced by plate bias Poly

SEM of poly-diffusion capacitor 1T-DRAM

Advanced 1T DRAM Cells Cell Plate Si Capacitor Insulator Storage Node Poly 2nd Field Oxide Refilling Poly Si Substrate Trench Cell Stacked-capacitor Cell Capacitor dielectric layer Cell plate Word line Insulating Layer IsolationTransfer gate Storage electrode GND

Static CAM Memory Cell

CAM in Cache Memory Address Decoder Hit Logic CAM ARRAY Input Drivers TagHit Address SRAM ARRAY Sense Amps / Input Drivers DataR/W

Introduction Non-volatile memories RAM Periphery circuits

Periphery  Decoders  Sense Amplifiers  Input/Output Buffers  Control / Timing Circuitry

Row Decoders Collection of 2 M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder

Hierarchical Decoders A 2 A 2 A 2 A 3 WL 0 A 2 A 3 A 2 A 3 A 2 A 3 A 3 A 3 A 0 A 0 A 0 A 1 A 0 A 1 A 0 A 1 A 0 A 1 A 1 A 1 1 Multi-stage implementation improves performance NAND decoder using 2-input pre-decoders

Dynamic Decoders Precharge devices V DD  GND WL A 0 A 0 GND A 1 A 1  WL 3 A 0 A 0 A 1 A V DD V V V 2-input NOR decoder 2-input NAND decoder Active low inputs (all are high except for the selected WL which is low)

4-input pass-transistor based column decoder Advantages: speed (t pd does not add to overall memory access time) Only one extra transistor in signal path Disadvantage: Large transistor count 2-input NOR decoder A 0 S 0 BL A 1 S 1 S 2 S 3 D

4-to-1 tree based column decoder Number of devices drastically reduced Delay increases quadratically with # of sections; prohibitive for large decoders buffers progressive sizing combination of tree and pass transistor approaches Solutions: BL D A 0 A 0 A 1 A 1

Decoder for circular shift- register

Sense Amplifiers t p C  V  I av = make  V as small as possible smalllarge Idea: Use Sense Amplifer output input s.a. small transition

Differential Sense Amplifier Directly applicable to SRAMs M 4 M 1 M 5 M 3 M 2 V DD bit SE Out y

Differential Sensing ― SRAM

Latch-Based Sense Amplifier (DRAM) Initialized in its meta-stable point with EQ Once adequate voltage gap created, sense amp enabled with SE Positive feedback quickly forces output to a stable operating point. EQ V DD BL SE

Charge-Redistribution Amplifier Concept M 2 M 3 M 1 V L V S V ref C small C large Transient Response

Charge-Redistribution Amplifier― EPROM SE V DD WLC Load Cascode device Column decoder EPROM array BL WL V casc Out C out C col C BL M 1 M 2 M 3 M 4

Single-to-Differential Conversion How to make a good V ref ?

Open bitline architecture with dummy cells C S C S C S C S BLL LL 1 L 0 R 0 C S R 1 C S L … … BLR V DD SE EQ Dummy cell

DRAM Read Process with Dummy Cell V BL t (ns) reading V SE EQWL t (ns) control signals V BL t (ns) reading 1

Voltage Regulator - + V DD V REF V bias M drive M V DL V V REF Equivalent Model

Charge Pump Q=Cpump (VDD-Vt) - -

DRAM Timing

SDRAM Timing A chunk of data is processed at the same time  effective when data is written in large sequential blocks

RDRAM Architecture memory array mux/demux network Data bus Clocks Column Row demux packet dec. Bus k k x l demux Rambus DRAM to reduce the access time Synch. DRAM Operates at uP clock speed up to 1.6 GB/sec bandwidth Highly parallel: A large number of bits can be read/write at the same time  interface ; fast and synch

Address Transition Detection DELAY t d A 0 t d A 1 t d A N 2 1 V DD ATD …

Introduction Non-volatile memories RAM Periphery Reliability

Reliability and Yield

Sensing Parameters in DRAM From [Itoh01] 4K K1M16M256M4G64G Memory Capacity (bits/chip) C D, Q S, C S, V DD, V smax C D(1F) C S Q S(1C) V smax(mv) V DD(V) Q S = C S V DD /2 V smax = Q S /(C S 1 C D )

Noise Sources in 1T DRam C cross electrode a -particles leakage C S WL BL substrate Adjacent BL C WBL

Open Bit-line Architecture —Cross Coupling Sense Amplifier C WL 1 BL C C WBL C CC WL 0 C C BL CC WL D D 0 1 BL EQ

Folded-Bitline Architecture

Transposed-Bitline Architecture

Alpha-particles (or Neutrons) 1 Particle ~ 1 Million Carriers WL BL V DD n 1 a -particle SiO

Yield Yield curves at different stages of process maturity (from [Veendrick92])

Redundancy Memory Array Column Decoder Row Decoder Redundant rows Redundant columns Row Address Column Address Fuse Bank :

Error-Correcting Codes Example: Hamming Codes with e.g. B3 Wrong = 3

Redundancy and Error Correction

Sources of Power Dissipation in Memories PERIPHERY ROW DEC selected non-selected CHIP COLUMN DEC nC DE V INT f mC DE V INT f C PT V INT f I DCP ARRAY m n m(n - 1)i hld mi act V DD V SS I DD = Σ C i Δ V i f +Σ+Σ I DCP From [Itoh00]

Data Retention in SRAM (A) SRAM leakage increases with technology scaling

Suppressing Leakage in SRAM SRAM cell SRAM cell SRAM cell V DD,int V DD V V DDL V SS,int sleep SRAM cell SRAM cell SRAM cell V DD,int sleep low-threshold transistor Reducing the supply voltage Inserting Extra Resistance

Data Retention in DRAM From [Itoh00]

Case Studies SRAM Flash Memory

4 Mbit SRAM Hierarchical Word-line Architecture

Bit-line Circuitry Bit-line load Block select ATD BEQ LocalWL Memory cell I/O line I/O B/T CD Sense amplifier CD I/O B/T

Sense Amplifier (and Waveforms) BS I/OI/O DATA Block selectATD BSSA BS SEQ De i I/O Lines Address Data-cut ATD BEQ SEQ DATA Vdd GND SA, SA Vdd GND

1 Gbit Flash Memory From [Nakamura02]

Writing Flash Memory Read level (4.5 V) Number of cells V1V2V Vt of memory cells 3V4V Evolution of thresholds Final Distribution From [Nakamura02]

125mm 2 1Gbit NAND Flash Memory 10.7mm 11.7mm 2kB Page buffer & cacheCharge pump bit lines 32 word lines x 1024 blocks From [Nakamura02]

125mm 2 1Gbit NAND Flash Memory Technology 0.13  m p-sub CMOS triple-well 1poly, 1polycide, 1W, 2Al Cell size  m2 Chip size 125.2mm2 Organization 2112 x 8b x 64 page x 1k block Power supply 2.7V-3.6V Cycle time 50ns Read time 25  s Program time 200  s / page Erase time 2ms / block Technology 0.13  m p-sub CMOS triple-well 1poly, 1polycide, 1W, 2Al Cell size  m2 Chip size 125.2mm2 Organization 2112 x 8b x 64 page x 1k block Power supply 2.7V-3.6V Cycle time 50ns Read time 25  s Program time 200  s / page Erase time 2ms / block From [Nakamura02]

Semiconductor Memory Trends (up to the 90’s) Memory Size as a function of time: x 4 every three years

Semiconductor Memory Trends (updated) From [Itoh01]

Trends in Memory Cell Area From [Itoh01]

Future generations Very specialized technologies for stand alone memories  expensive Reliability is going to be a very important issue (SER) particularly for SRAMs and DRAMs Power is going to be the limiting factor particularly when it comes to standby currents Embedded memories is the prominent market thrust driven by all mobile/SoC applications