EEE2243 Digital System Design Chapter 4: Datapath Components by Muhazam Mustapha, February 2012

Learning Outcome By the end of this chapter, students are expected to understand the design, operation and block diagram of the following datapath components: –Register and register file –Shifter, counter, incrementer –Comparator –Adder, subtractor, multiplier

Chapter Content Register and Register File Shifter Modular Verilog Counter, Incrementer and Timer Comparator Adder, Subtractor, Multiplier

Datapath Component

Datapath component is a collection of memory and computation circuits that when put together and with proper control, can perform a larger scale of operation In previous chapters we have covered many of the components like: –Counter, Decoder and Multiplexer We will go into more details on the components that we already covered, and some new ones Vahid 4.1 pg 167

Register & Register File

Register A collection of flip-flops used to store data or maintain states in FSM In normal operations registers load on every clock pulse In datapath operation we need to set the register to load only when we want it to D Q D Q D Q D Q I2I3 Q2Q3Q1Q0 I1I0 clk 4-bit register load

Conditional Parallel Load In datapath operation register load operations are mostly parallel – only communication applications use serial mode load The load operation however, needs to be done when a LOAD signal is on This can be done in BEHAVIORAL approach using a 2-to-1 mux at D input –diagram on next slide The LOAD signal will determine either the flip- flop is to be loaded with new data or maintain current data by feedback

Conditional Parallel Load Vahid Figure 4.1 pg 169

Parallel Register Example

Shift Register In some applications, datapath operations need to perform serial computation This can be done using shift register Shift register operates by transferring flip-flop’s bit content to neighboring flip-flop in the same register while maintaining the conditional LOAD operation –Both SHIFT and LOAD operation are conditional –Some shift registers may have parallel LOAD operation as well Vahid pg 173

Shift Register shr_in Implementation: Connect flip-flop output to next flip-flop’s input Datapath Implementation Vahid Figure 4.10 pg 174

Rotate Register Bit coming out from one end will go into the other end Exercise: Draw out yourself the datapath implementation of rotate register Vahid Figure 4.11 pg 174

More Complicated Register Behavioral control of register by mux can already provide us a good number of features The following is a register with 2 control line: Functions: Operation Maintain present value Parallel load Shift right Load zero s s Vahid Figure 4.13 pg 176

Boolean Algebra Approach Register Design For some performance improvement, Boolean algebra design can be used; Try the following: Q2Q1Q0Q3 Q2Q1Q0Q3 I2I1I0I3 I2I1I0I3 s1 shr_in shr shl ld s0 shl_in s1 = ld’*shr’*shl + ld’*shr*shl’ + ld’*shr*shl s0 = ld’*shr’*shl + ld combi- national circuit Vahid pg

Register File In some designs we may require too many registers In such designs we might be using too many wires and may cause congestions or we may exceed the synthesizable limit for no. lines This can be solve by sharing lines – BUS The registers will be accessed through address and only connect to the bus lines when selected There will be many High-Z capable connections Vahid 4.10 pg 225

Register File W_data W_addr W_en R_data R_addr R_en 4x32 register file Vahid Figure 4.78 (modified), 4.79, 4.80

Register File Timing Diagram W_data W_addr W_en R_data R_addr R_en 4x32 register file Vahid Figure 4.82

Shifter

Shift register makes transfer between memory elements (flip-flop) to achieve shifting effect We can speed up the shift process if we remove the memory element since we don’t have to wait for the clock pulse to actually make the shift happens This fast shifting is required especially if the shifting is done to get the effect of multiplication by powers of 2 Shifter is the datapath component that does this with only multiplexers – no D flip-flop Vahid 4.8 pg 210

Shifter <<1 Symbol i2 q3q2q1q0 in i3i1i0 Left shifter in sh i3 q3q2q1q0 i2i1i0 Shifter with left shift or no shift inL i3 q3q2q1q0 i2i1i0 inR 20 s0 s1 shL shR Shifter with left shift, right shift, and no shift

Modular Verilog

Module Instantiation In Verilog modules can be defined and instantiated Wires can be used to interconnect modules and other components in the design The calling syntax is as follows: Instantiated_Module Name_of_this_instance(.Instantiated_Parameter_1(local_variable_1),.Instantiated_Parameter_2(local_variable_2),... );

Module Instantiation Let’s take the Half-Adder circuit in Chapter 1 to be instantiated in a design of Full-Adder as given in Adder Sub-section of this chapter The Half-Adder code: module HalfAdder(a, b, sum, carry); input a, b; output sum, carry; assign sum = a ^ b; assign carry = a & b; endmodule a b sum carry

Module Instantiation The Full-Adder design to make use of the Half- Adder: Wires Half-Adder Instances Wires

Module Instantiation module HalfAdder(a, b, sum, carry); input a, b; output sum, carry; assign sum = a ^ b; assign carry = a & b; endmodule module FA(a, b, cin, s, cout); input a, b, cin; output s, cout; wire tempSum, finSum, c1, c2; HA1 First (.a(a),.b(b),.sum(tempSum),.carry(c1)); HA1 Second(.a(tempSum),.b(cin),.sum(finSum),.carry(c2)); assign s = finSum; assign cout = c1 | c2; endmodule

Counter, Incrementer & Timer

Modularized Counter In the previous chapter we designed counter to just count the clock pulses As a datapath component, counter needs control lines so it can be integrated into a bigger design We will see more modularized counter design as a datapath component Vahid 4.9 pg 215

Modularized Up Counter ld 4-bit register Ctc cnt 4-bit up-counter +1 Regular up counter can be modularized to have –Registers to keep count value –Incrementer –Terminal count detector – for up counter, it is an AND gate as we assume the terminal count is all ones cnt tcC 4-bit up-counter Vahid pg 216

Incrementer Incrementer is an adder whose job is to always add 1 to its input It is natural to design incrementer using FULL adder setting one of the addend to a constant 1 However, a better design will be using cascaded HALF adders with a 1 addend at LSB –This can be done since the second addend is basically zero (except at LSB), hence lifting its need as one of full adder inputs which means we can reduce the full adder to half adder –This results in a simpler circuit

Incrementer equivalent a3 cos FA co a2 s3s2s1 ciba cos FA ba a1 cos FA ciba s0 a00 cos FA ciba a3 cos HA co a2 s3s2s1 ba cos HA ba a1 cos HA ba s0 a01 cos HA ba equivalent

Modularized Down Counter Modular down counter may have –Registers to keep count value –Decrementer –Terminal count detector – for down counter, it is a NOR gate as we assume the terminal count is all zeros ld 4-bit register Ctc cnt 4-bit down-counter –1

Decrementer Decrementer is a subtractor whose job is to always minus 1 from its input Decrementer can be designed using full adder by setting one of the addend to all 1-s –This is true because subtracting by 1 is equivalent to adding with 2’s complement of 1, and 2’s complement of 1 is a binary number with all 1-s a3 cos FA co a2 s3s2s1 ciba cos FA ba a1 cos FA ciba s0 a00 cos FA ciba There is a way to design decrementer using HALF SUBTRACTOR (HS), but we are not going into detail about it as it is not so behavioral design friendly as HS is not well accepted as datapath component

Up/Down Counter To make it a more useful counter in datapath circuit, we might want to add more control to the counter One possible control is to control the direction of counting – either up or down This can be done by adding DIR (direction) control line DIR will be used to multiplex the: –feedback input to register – either from incrementer or decrementer –terminal count detecter – either from AND or NOR gate

Up/Down Counter 4-bit register Ctc dir 4-bit up/down counter 44 – x bit 2 x 1 Vahid pg 217

Timer Timer is just a counter that is clocked by a KNOWN clock frequency Normally it is an up counter, with additional controls of: –count (CNT) – only count if CNT is 1 –clear (CLR) – synchronously reset timer if CLR is 1 Vahid pg 222

Comparator

Equality Comparator Comparator is a datapath component that test the values of its two inputs for equality, less than or greater condition Equality comparator just test for equality Obviously equality test can be done by comparing the equality of the two inputs bit-by- bit Comparison can be done bit-by-bit by 2-input XNOR gates, then combine the output by an AND Vahid 4.4 pg 191

Equality Comparator a3b3a2b2a1b1a0b0 eq (a) (b) a3a2a1a0b3 eq b2b1b0 4-bit equality comparator Example comparing 0110 to 0111:

Magnitude Comparator Magnitude comparator gives all possible equality, less than or greater than condition Algorithm to compare A and B starting at MSB: –If the bit are the same repeat to compare next LSB –Else if bit A is 1 and bit B is 0 then stop by giving condition A > B –Else if bit A is 0 and bit B is 1 then stop by giving condition A < B A=1011B= Equal Equal Unequal So A > B Vahid pg 192

Cascade Comparator From the algorithm in the previous slide, we can formulate one stage of the bit-by-bit comparison using the following circuit: a b from previous stage in_eq in_gt in_lt to next stage out_gt out_lt out_eq

Cascade Comparator At each stage: –out_gt = in_gt + (in_eq * a * b) A>B (so far) if already determined in higher stage, or if higher stages equal but in this stage a=1 and b=0 –out_lt = in_lt + (in_eq * a * b) A<B (so far) if already determined in higher stage, or if higher stages equal but in this stage a=0 and b=1 –out_eq = in_eq * (a XNOR b) A=B (so far) if already determined in higher stage and in this stage a=b too in_gt in_eq in_lt out_gt out_eq out_lt Igt Ieq Ilt Stage 3 a3b3 ab in_gt in_eq in_lt out_gt out_eq out_lt Stage 2 a2b2 ab in_gt in_eq in_lt out_gt out_eq out_lt Stage 1 a1b1 ab in_gt in_eq in_lt out_gt out_eq out_lt AgtB AeqB AltB Stage 0 a0b0 ab

Cascade Comparator Example comparing 1011 to 1001: in_gt in_eq in_lt out_gt out_eq out_lt Stage3 a3b3 ab in_gt in_eq in_lt out_gt out_eq out_lt Stage2 a2b2 ab in_gt in_eq in_lt out_gt out_eq out_lt Stage1 a1b1 ab in_gt in_eq in_lt out_gt out_eq out_lt AgtB AeqB AltB Stage0 a0b ab (a) = in_gt in_eq in_lt out_gt out_eq out_lt Stage3 a3b3 ab in_gt in_eq in_lt out_gt out_eq out_lt Stage2 a2b2 ab in_gt in_eq in_lt out_gt out_eq out_lt Stage1 a1b1 ab in_gt in_eq in_lt out_gt out_eq out_lt AgtB AeqB AltB Stage0 a0b ab (b) =

Cascade Comparator Example comparing 1011 to 1001 (continue): in_gt in_eq in_lt out_gt out_eq out_lt Stage3 a3b3 ab in_gt in_eq in_lt out_gt out_eq out_lt Stage2 a2b2 ab in_gt in_eq in_lt out_gt out_eq out_lt Stage1 a1b1 ab in_gt in_eq in_lt out_gt out_eq out_lt AgtB AeqB AltB Stage0 a0b ab (c) > in_gt in_eq in_lt out_gt out_eq out_lt Stage3 a3b3 ab in_gt in_eq in_lt out_gt out_eq out_lt Stage2 a2b2 ab in_gt in_eq in_lt out_gt out_eq out_lt Stage1 a1b1 ab in_gt in_eq in_lt out_gt out_eq out_lt AgtB AeqB AltB Stage0 a0b ab (d)

Comparator Application Minimum of 2 numbers: MIN Igt Ieq Ilt AgtB AeqB AltB A AB B 8-bit magnitude comparator s I1I0 2x1 mux 8-bit C C AB Min (a) (b)

Adder, Subtractor & 2’s Complement, Multiplier

Half Adder Half adders add two 1 bit inputs, then generate 1 bit sum and 1 bit carry ab c cs ab s Half Adder s c b a InputsOutputs Truth TableBlock Diagram Circuit Vahid 4.3 pg 181

Full Adder Full adders add two 1 bit inputs and one carry-in then generate 1 bit sum and 1 bit carry-out cos ab Full Adder Truth Table Block Diagram Circuits s co ci b a InputsOutputs ci co ba s Full adder

Larger Adder – Ripple Carry Arbitrary no. bit adder can be constructed by cascading half adder and full adder as follows: This is called carry ripple technique as the carry is being transferred from one adder to the next one a3 cos FA co b3a2b2 s3s2s1 ciba cos FA ba a1b1 cos FA ciba s0 a0b0 cos HA ba a3 cos FA co b3a2b2 s3s2s1 ciba cos FA ba a1b1 cos FA ciba s0 a0b00 cos FA ciba OR

Cascading Adders a3a2a1a0b3 s3s2s1s0co s7s6s5s4co ci b2b1b0 a7a6a5a4b7b6b5b4 4-bit adder a3a2a1a0b3 s3s2s1s0 s3s2s1s0 co ci b2b1b0 a3a2a1a0b3b2b1b0 4-bit adder a7.. a0b7.. b0 s7.. s0co ci 8-bit adder

Subtractor a3 cos FA co b3 a2 b2 s3s2s1 ciba cos FA ba a1 b1 cos FA ciba s0 a0 b0 cos FA ciba sub/add

2’s Complement 2’s comp circuit can be constructed from the circuit in the previous slide by setting the minuend to 0 (zero) Or the following dedicated 2’s comp circuit can be used:

Overflow Detection In bit size limited addition, overflow happens when two same sign numbers are added but results in a different sign In a 4 bit Boolean addition of s 3 s 2 s 1 s 0 = a 3 a 2 a 1 a 0 +b 3 b 2 b 1 b 0, this can be expressed as: Vahid pg 205 Another way to detect overflow is by comparing the carry into and out of the MSB during the addition – if the two are the same there is no overflow

Multiplication – Array Style 1 bit multiplication is identical to Boolean AND operation – this allows us to mimic multiplication using Boolean gates Vahid 4.5 pg 195

Multiplication – Array Style Generalization:

Multiplication – Array Style Implementation by AND gate array: pp1 pp2 pp3 pp4 Vahid Figure 4.45