Wen-Hao Liu 1, Yih-Lang Li 1, and Kai-Yuan Chao 2 1 Department of Computer Science, National Chiao-Tung University, Hsin-Chu, Taiwan 2 Intel Architecture.

Slides:



Advertisements
Similar presentations
THERMAL-AWARE BUS-DRIVEN FLOORPLANNING PO-HSUN WU & TSUNG-YI HO Department of Computer Science and Information Engineering, National Cheng Kung University.
Advertisements

OCV-Aware Top-Level Clock Tree Optimization
Optimization of Placement Solutions for Routability Wen-Hao Liu, Cheng-Kok Koh, and Yih-Lang Li DAC’13.
Topology-Aware Buffer Insertion and GPU-Based Massively Parallel Rerouting for ECO Timing Optimization Yen-Hung Lin, Yun-Jian Lo, Hian-Syun Tong, Wen-Hao.
Hsi-An Chien Ting-Chi Wang Redundant-Via-Aware ECO Routing ASPDAC2014.
Wen-Hao Liu1, Yih-Lang Li, and Cheng-Kok Koh Department of Computer Science, National Chiao-Tung University School of Electrical and Computer Engineering,
3D-STAF: Scalable Temperature and Leakage Aware Floorplanning for Three-Dimensional Integrated Circuits Pingqiang Zhou, Yuchun Ma, Zhouyuan Li, Robert.
Meng-Kai Hsu, Sheng Chou, Tzu-Hen Lin, and Yao-Wen Chang Electronics Engineering, National Taiwan University Routability Driven Analytical Placement for.
Ripple: An Effective Routability-Driven Placer by Iterative Cell Movement Xu He, Tao Huang, Linfu Xiao, Haitong Tian, Guxin Cui and Evangeline F.Y. Young.
Paul Falkenstern and Yuan Xie Yao-Wen Chang Yu Wang Three-Dimensional Integrated Circuits (3D IC) Floorplan and Power/Ground Network Co-synthesis ASPDAC’10.
Coupling-Aware Length-Ratio- Matching Routing for Capacitor Arrays in Analog Integrated Circuits Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang and Hui-Fang.
Multiobjective VLSI Cell Placement Using Distributed Simulated Evolution Algorithm Sadiq M. Sait, Mustafa I. Ali, Ali Zaidi.
Layer Assignment Algorithm for RLC Crosstalk Minimization Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong Tsinghua University.
38 th Design Automation Conference, Las Vegas, June 19, 2001 Creating and Exploiting Flexibility in Steiner Trees Elaheh Bozorgzadeh, Ryan Kastner, Majid.
Power-Aware Placement
1 University of Freiburg Computer Networks and Telematics Prof. Christian Schindelhauer Mobile Ad Hoc Networks Theory of Data Flow and Random Placement.
Supply Voltage Degradation Aware Analytical Placement Andrew B. Kahng, Bao Liu and Qinke Wang UCSD CSE Department {abk, bliu,
A Resource-level Parallel Approach for Global-routing-based Routing Congestion Estimation and a Method to Quantify Estimation Accuracy Wen-Hao Liu, Zhen-Yu.
Metal Layer Planning for Silicon Interposers with Consideration of Routability and Manufacturing Cost W. Liu, T. Chien and T. Wang Department of CS, NTHU,
CDCTree: Novel Obstacle-Avoiding Routing Tree Construction based on Current Driven Circuit Model Speaker: Lei He.
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig 1 FLUTE: Fast Lookup Table Based RSMT Algorithm.
Chih-Hung Lin, Kai-Cheng Wei VLSI CAD 2008
MGR: Multi-Level Global Router Yue Xu and Chris Chu Department of Electrical and Computer Engineering Iowa State University ICCAD
A Topology-based ECO Routing Methodology for Mask Cost Minimization Po-Hsun Wu, Shang-Ya Bai, and Tsung-Yi Ho Department of Computer Science and Information.
Area-I/O Flip-Chip Routing for Chip-Package Co-Design Progress Report 方家偉、張耀文、何冠賢 The Electronic Design Automation Laboratory Graduate Institute of Electronics.
Authors: Jia-Wei Fang,Chin-Hsiung Hsu,and Yao-Wen Chang DAC 2007 speaker: sheng yi An Integer Linear Programming Based Routing Algorithm for Flip-Chip.
CAFE router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles Y. Kohira and A. Takahashi School of Computer Science.
Global Routing.
Pattern Selection based co-design of Floorplan and Power/Ground Network with Wiring Resource Optimization L. Li, Y. Ma, N. Xu, Y. Wang and X. Hong WuHan.
1 Coupling Aware Timing Optimization and Antenna Avoidance in Layer Assignment Di Wu, Jiang Hu and Rabi Mahapatra Texas A&M University.
Block-level 3D IC Design with Through-Silicon-Via Planning Dae Hyun Kim, Rasit Onur Topaloglu, and Sung Kyu Lim Department of Electrical and Computer Engineering,
TSV-Aware Analytical Placement for 3D IC Designs Meng-Kai Hsu, Yao-Wen Chang, and Valerity Balabanov GIEE and EE department of NTU DAC 2011.
Solving Hard Instances of FPGA Routing with a Congestion-Optimal Restrained-Norm Path Search Space Keith So School of Computer Science and Engineering.
Low-Power Gated Bus Synthesis for 3D IC via Rectilinear Shortest-Path Steiner Graph Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, and Shih-Hung Weng UC San.
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig 1 EECS 527 Paper Presentation High-Performance.
Archer: A History-Driven Global Routing Algorithm Mustafa Ozdal Intel Corporation Martin D. F. Wong Univ. of Illinois at Urbana-Champaign Mustafa Ozdal.
An Efficient Clustering Algorithm For Low Power Clock Tree Synthesis Rupesh S. Shelar Enterprise Microprocessor Group Intel Corporation, Hillsboro, OR.
BSG-Route: A Length-Matching Router for General Topology T. Yan and M. D. F. Wong University of Illinois at Urbana-Champaign ICCAD 2008.
New Modeling Techniques for the Global Routing Problem Anthony Vannelli Department of Electrical and Computer Engineering University of Waterloo Waterloo,
Efficient Multi-Layer Obstacle- Avoiding Rectilinear Steiner Tree Construction Chung-Wei Lin, Shih-Lun Huang, Kai-Chi Hsu,Meng-Xiang Li, Yao-Wen Chang.
Bus-Pin-Aware Bus-Driven Floorplanning B. Wu and T. Ho Department of Computer Science and Information Engineering NCKU GLSVLSI 2010.
A Routing Approach to Reduce Glitches in Low Power FPGAs Quang Dinh, Deming Chen, Martin D. F. Wong Department of Electrical and Computer Engineering University.
AUTOMATIC BUS PLANNER FOR DENSE PCBS Hui Kong, Tan Yan and Martin D.F. Wong Department of Electrical and Computer Engineering, University of Illinois at.
Placement. Physical Design Cycle Partitioning Placement/ Floorplanning Placement/ Floorplanning Routing Break the circuit up into smaller segments Place.
IO CONNECTION ASSIGNMENT AND RDL ROUTING FOR FLIP-CHIP DESIGNS Jin-Tai Yan, Zhi-Wei Chen 1 ASPDAC.2009.
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 6: Detailed Routing © KLMH Lienig 1 What Makes a Design Difficult to Route Charles.
GLARE: Global and Local Wiring Aware Routability Evaluation Yaoguang Wei1, Cliff Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi Reddy,
ARCHER:A HISTORY-DRIVEN GLOBAL ROUTING ALGORITHM Muhammet Mustafa Ozdal, Martin D. F. Wong ICCAD ’ 07.
Optimization of Wavelength Assignment for QoS Multicast in WDM Networks Xiao-Hua Jia, Ding-Zhu Du, Xiao-Dong Hu, Man-Kei Lee, and Jun Gu, IEEE TRANSACTIONS.
1 Efficient Obstacle-Avoiding Rectilinear Steiner Tree Construction Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang National Taiwan.
Configurable Multi-product Floorplanning Qiang Ma, Martin D.F. Wong, Kai-Yuan Chao ASP-DAC 2010.
A Negotiated Congestion based Router for Simultaneous Escape Routing Q.Ma, T.Yan and Martin D.F. Wong Department of Electrical and Computer Engineering.
1 A Min-Cost Flow Based Detailed Router for FPGAs Seokjin Lee *, Yongseok Cheon *, D. F. Wong + * The University of Texas at Austin + University of Illinois.
Timing-Driven Routing for FPGAs Based on Lagrangian Relaxation
Simultaneous Analog Placement and Routing with Current Flow and Current Density Considerations H.C. Ou, H.C.C. Chien and Y.W. Chang Electronics Engineering,
Routing Tree Construction with Buffer Insertion under Obstacle Constraints Ying Rao, Tianxiang Yang Fall 2002.
Maze Routing Algorithms with Exact Matching Constraints for Analog and Mixed Signal Designs M. M. Ozdal and R. F. Hentschke Intel Corporation ICCAD 2012.
Routability-driven Floorplanning With Buffer Planning Chiu Wing Sham Evangeline F. Y. Young Department of Computer Science & Engineering The Chinese University.
LEMAR: A Novel Length Matching Routing Algorithm for Analog and Mixed Signal Circuits H. Yao, Y. Cai and Q. Gao EDA Lab, Department of CS, Tsinghua University,
Efficient Resource Allocation for Wireless Multicast De-Nian Yang, Member, IEEE Ming-Syan Chen, Fellow, IEEE IEEE Transactions on Mobile Computing, April.
High-Performance Global Routing with Fast Overflow Reduction Huang-Yu Chen, Chin-Hsiung Hsu, and Yao-Wen Chang National Taiwan University Taiwan.
An Exact Algorithm for Difficult Detailed Routing Problems Kolja Sulimma Wolfgang Kunz J. W.-Goethe Universität Frankfurt.
A Novel Timing-Driven Global Routing Algorithm Considering Coupling Effects for High Performance Circuit Design Jingyu Xu, Xianlong Hong, Tong Jing, Yici.
Partial Reconfigurable Designs
Constraint-Based Routing
Multi-Commodity Flow Based Routing
Placement and Routing With Congestion Control
Off-path Leakage Power Aware Routing for SRAM-based FPGAs
Communication Driven Remapping of Processing Element (PE) in Fault-tolerant NoC-based MPSoCs Chia-Ling Chen, Yen-Hao Chen and TingTing Hwang Department.
Under a Concurrent and Hierarchical Scheme
Presentation transcript:

Wen-Hao Liu 1, Yih-Lang Li 1, and Kai-Yuan Chao 2 1 Department of Computer Science, National Chiao-Tung University, Hsin-Chu, Taiwan 2 Intel Architecture Group, Intel Corporation,Hillsboro,OR High-Quality Global Routing for Multiple Dynamic Supply Voltage Designs

Outline Introduction Problem Description Design Flow of MDSV-Based Global Routing Power Domain-Aware Minimum Spanning Tree Power Domain-Aware Routing (PDR) Experimental Results Conclusion

Introduction Total power consumption generally includes both dynamic power and static power. Static power is produced by leakage current Dynamic power is produced by the switching activities of the device In modern circuit design, most of the total power consumption is dynamic power consumption, which is proportional to the square of supply voltage V dd.

Introduction Multiple supply voltage (MSV) It effectively reduces dynamic power with a sophisticated control on different function units' voltages. Power domain floorplan structures may be either block- based, or non-block-based structure.

Introduction Multiple dynamic supply voltage (MDSV) The supply voltage of each power domain dynamically changes according to the power mode. In some power modes, such as waiting and sleeping modes, some power domains may even be shut down completely to save power.

Problem Description Traditional Global Routing Problem The global routing is formulated as the routing problem on a grid graph G(V, E), where V denotes the set of grid cells, and E denotes the set of grid edges. The capacity c(e) of a grid edge e indicates the number of routing tracks that cross the abutting boundary. The number of wires that pass through grid edge e is called the demand of the grid edge d(e). The overflow of a grid edge e (overflow(e)) is defined as the amount of demand in excess of capacity. The optimization order of global routing problem is to minimize the total overflow, total wirelength, and runtime.

Problem Description The Routing Limitations of Multiple Dynamic Supply Voltage Designs The path cannot pass through any domains in which its metal can be changed at the different product configurations. If the wire length of the path exceeds a threshold value, repeaters must be inserted on the routing path to prevent signal degradation. As the net is active, the repeaters must be placed in the non-shutdown power domains.

Problem Description The Routing Limitations of Multiple Dynamic Supply Voltage Designs Definition 1. Repeater-free region: In any power mode of an MDSV design, if a net n i is active when a power domain p is shut down, p is the repeater-free region associated with net n i.

Problem Description The Routing Limitations of Multiple Dynamic Supply Voltage Designs Definition 2. Driving length constraint: The driving length of a repeater is the maximum wire length that can be driven by the repeater without causing signal distortion or violating design timing requirements.

Problem Description MDSV-based global routing problem Input: Given a 5-tuple (G, PDS, M, F, N), G represents a grid graph PDS represents a set of block-based-structure power domains M denotes a set of power modes F denotes a set of forbidden regions. N={n 1,...,n m } represents a set of nets Objective: Minimized total overflow first and then total wirelength. Constraint: Avoids passing through the forbidden regions Driving length constraint.

Design Flow of MDSV-Based Global Routing

Power Domain-Aware Minimum Spanning Tree This work adopts power domain-aware minimum spanning tree (PDMST) instead of traditional minimum spanning tree(MST) and Steiner minimum tree (SMT) for use as the initial tree topology for each net. The cost of a PDMST is sum of its wire length and the penalty for crossing power domains.

Power Domain-Aware Routing (PDR) Notations for PDR: P d,u is a routing path from driver d to node u M(u, n i ) is the minimum Euclidean distance between node u and the boundary of the nearest non-shutdown region of net n i W(P d,u, u, n i ) is the wirelength of wire segments of P d,u from u to the boundary of a non-shutdown region of n i

PPPDR problem formulation Given a 7-tuple (d, r, X, G, NSR, RFR, Lx) d: driver r: receiver X: power domain G: congestion graph NSR: nonshutdown regions RFR: repeater-free regions Lx: driving length constraints Point-to-Point PDR (PPPDR)

A path P d,u is considered feasible if the following equation is true: E u,r is an u-to-r path that is estimated by identifying a least- cost monotonic path (MP). Point-to-Point PDR (PPPDR) Look-Ahead Path Selection

If only one path is feasible, the feasible path is selected. If both paths are feasible, the least-cost path is selected. If neither path is feasible, the path with shorterW(P d,u, u, n i ) is reserved Point-to-Point PDR (PPPDR) Look-Ahead Path Selection

Build the table to look up W(E u,r, u, n i ) for each node in the selected path in constant time the time complexity: from O(|V|) to O(|1|). Four monotonic routings from r to four corners of SR max determine the least-cost MPs from r to any node in SR max. Accelerating Path Selection by Look-Up Table

Multi-Source Multi-Target PDR (MMPDR) MMPDR is a tree-to-tree routing algorithm In MMPDR, a path P d,u, is regarded as a feasible path if the following equation holds; E u,Tt represents the globally least-cost MP from node u to sub-tree T t

Multi-Source Multi-Target PDR (MMPDR) Build a lookup table to pre-store the values of W( E u,Tt, u, ni) before MMPDR is performed (SR max ): searching region (B tar ): minimum rectangle that encloses the target tree T t Globally least-cost MPs from Tt to every node in SR max Four modified point-to-point monotonic routings from B bl to R tr, B br to R tl, B tl to R br and B tr to R bl.

Multi-Source Multi-Target PDR (MMPDR) The globally least-cost MP that connects a node to T t is the one with the least cost from the results obtained using four TPNMRs (tree-to-partial-nodes monotonic routing) The time complexity of TPNMR is O(|V|), and the time complexity for building the lookup table for MMPDR is also O(|V|). Finally, the worst time complexity of MMPDR is O(|V|+|V|log|V|))= O(|V|log|V|).

Experimental Results

Conclusion An MDSV-based global router that is based on the proposed PDR algorithm. Power domain-aware minimum spanning tree (PDMST) for use as the initial tree topology for each net, that can decrease the wirelength and the number of level shifters required of final routing result The proposed router can yield legally high-quality results under the routing limitation of MDSV designs, with an average wirelength improvement of 1% and runtime speedup by a factor of 1.92 relative to PRD-GR.

Thank You!