1 Copyright © Monash University ATM Switch Design Philip Branch Centre for Telecommunications and Information Engineering (CTIE) Monash University

Slides:



Advertisements
Similar presentations
ATM Switch Architectures
Advertisements

EECC694 - Shaaban #1 lec # 10 Spring Asynchronous Transfer Mode (ATM) ATM is a specific asynchronous packet-oriented information, multiplexing.
Quality of Service Requirements
1 ELEN 602 Lecture 18 Packet switches Traffic Management.
1 Omega Network The omega network is another example of a banyan multistage interconnection network that can be used as a switch fabric The omega differs.
Module 3.4: Switching Circuit Switching Packet Switching K. Salah.
1 Delta Network The delta network is one example of a multistage interconnection network that can be used as a switch fabric The delta network is an example.
What's inside a router? We have yet to consider the switching function of a router - the actual transfer of datagrams from a router's incoming links to.
Spring 2002CS 4611 Router Construction Outline Switched Fabrics IP Routers Tag Switching.
1 Performance Results The following are some graphical performance results out of the literature for different ATM switch designs and configurations For.
10 - Network Layer. Network layer r transport segment from sending to receiving host r on sending side encapsulates segments into datagrams r on rcving.
Chapter 10 Switching Fabrics. Outline Physical Interconnection Physical box with backplane Individual blades plug into backplane slots Each blade contains.
EE 122: Router Design Kevin Lai September 25, 2002.
ATM COMPONENTS Presented by: ANG BEE KEEWET CHONG SIT MEIWET LAI YIN LENGWET LEE SEANG LEIWET
Katz, Stoica F04 EECS 122: Introduction to Computer Networks Switch and Router Architectures Computer Science Division Department of Electrical Engineering.
Analysis of Input Queueing More complex system to analyze than output queueing case. In order to analyze it, we make a simplifying assumption of "heavy.
Pipelined Two Step Iterative Matching Algorithms for CIOQ Crossbar Switches Deng Pan and Yuanyuan Yang State University of New York, Stony Brook.
Localized Asynchronous Packet Scheduling for Buffered Crossbar Switches Deng Pan and Yuanyuan Yang State University of New York Stony Brook.
4: Network Layer4b-1 Router Architecture Overview Two key router functions: r run routing algorithms/protocol (RIP, OSPF, BGP) r switching datagrams from.
Chapter 4 Queuing, Datagrams, and Addressing
1 IP routers with memory that runs slower than the line rate Nick McKeown Assistant Professor of Electrical Engineering and Computer Science, Stanford.
Computer Networks Switching Professor Hui Zhang
An Integrated IP Packet Shaper and Scheduler for Edge Routers MSEE Project Presentation Student: Yuqing Deng Advisor: Dr. Belle Wei Spring 2002.
ATM SWITCHING. SWITCHING A Switch is a network element that transfer packet from Input port to output port. A Switch is a network element that transfer.
TO p. 1 Spring 2006 EE 5304/EETS 7304 Internet Protocols Tom Oh Dept of Electrical Engineering Lecture 9 Routers, switches.
Router Architecture Overview
Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 1 Packet Switches.
Switches and indirect networks Computer Architecture AMANO, Hideharu Textbook pp. 92~13 0.
Survey of Performance Analysis on Banyan Networks Written By Nathan D. Truhan Kent State University.
Univ. of TehranAdv. topics in Computer Network1 Advanced topics in Computer Networks University of Tehran Dept. of EE and Computer Engineering By: Dr.
Outline Packet switching paradigms Bridges and extended LANs Cell switching Switching hardware.
Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 1 ECSE-6600: Internet Protocols Informal Quiz #14 Shivkumar Kalyanaraman: GOOGLE: “Shiv RPI”
Computer Networks: Switching and Queuing Ivan Marsic Rutgers University Chapter 4 – Switching and Queuing Delay Models.
ISLIP Switch Scheduler Ali Mohammad Zareh Bidoki April 2002.
Case Study: The Abacus Switch CS Goals and Considerations Handles cell relay (fixed-size packets) Can be modified to handle variable-sized packets.
Final Chapter Packet-Switching and Circuit Switching 7.3. Statistical Multiplexing and Packet Switching: Datagrams and Virtual Circuits 4. 4 Time Division.
Shared Memory switches Masoud Sabaei Assistant professor Computer Engineering and Information Technology Department, Amirkabir University of Technology.
Forwarding.
21-Dec-154/598N: Computer Networks Cell Switching (ATM) Connection-oriented packet-switched network Used in both WAN and LAN settings Signaling (connection.
T. S. Eugene Ngeugeneng at cs.rice.edu Rice University1 COMP/ELEC 429 Introduction to Computer Networks Lecture 18: Quality of Service Slides used with.
Interconnect Networks Basics. Generic parallel/distributed system architecture On-chip interconnects (manycore processor) Off-chip interconnects (clusters.
Buffered Crossbars With Performance Guarantees Shang-Tse (Da) Chuang Cisco Systems EE384Y Thursday, April 27, 2006.
1 IEX8175 RF Electronics Avo Ots telekommunikatsiooni õppetool, TTÜ raadio- ja sidetehnika inst.
Lecture Note on Switch Architectures. Function of Switch.
1 A quick tutorial on IP Router design Optics and Routing Seminar October 10 th, 2000 Nick McKeown
1 Buffering Strategies in ATM Switches Carey Williamson Department of Computer Science University of Calgary.
Packet Switch Architectures The following are (sometimes modified and rearranged slides) from an ACM Sigcomm 99 Tutorial by Nick McKeown and Balaji Prabhakar,
Virtual-Channel Flow Control William J. Dally
Spring 2000CS 4611 Router Construction Outline Switched Fabrics IP Routers Extensible (Active) Routers.
Network Layer4-1 Chapter 4 Network Layer All material copyright J.F Kurose and K.W. Ross, All Rights Reserved Computer Networking: A Top Down.
Univ. of TehranIntroduction to Computer Network1 An Introduction to Computer Networks University of Tehran Dept. of EE and Computer Engineering By: Dr.
CS 4594 Broadband Switching Elements and Fabrics.
Input buffered switches (1)
Providing QoS in IP Networks
Structure of a switch We use switches in circuit-switched and packet- switched networks. In this section, we discuss the structures of the switches used.
Univ. of TehranIntroduction to Computer Network1 An Introduction to Computer Networks University of Tehran Dept. of EE and Computer Engineering By: Dr.
Data and Computer Communications 8 th and 9 th Edition by William Stallings Chapter 10 – Circuit Switching and Packet Switching.
Switching Techniques In large networks there might be multiple paths linking sender and receiver. Information may be switched as it travels through various.
Chapter 4: Network Layer
Packet Switching (basics)
Bridges and Extended LANs
Switching Techniques.
Router Construction Outline Switched Fabrics IP Routers
Delta Network The delta network is one example of a multistage interconnection network that can be used as a switch fabric The delta network is an example.
EE 122: Lecture 7 Ion Stoica September 18, 2001.
Computer Networks: Switching and Queuing
Introduction to Packet Scheduling
Chapter 4: Network Layer
Switch Performance Analysis and Design Improvements
Introduction to Packet Scheduling
Presentation transcript:

1 Copyright © Monash University ATM Switch Design Philip Branch Centre for Telecommunications and Information Engineering (CTIE) Monash University

2 Copyright © Monash University ATM Switching Outline Switching terms and requirements Switch Architectures –cross bar, multiple bus, multistage –routing in multistage switches Buffering schemes in switches Buffer management Performance Measures

3 Copyright © Monash University ATM Switching Terms Switching Switching Element Switching Fabric Switching System

4 Copyright © Monash University ATM Switch Requirements Flexible switching rates Broadcast and Multicast Low cell loss probability Cell Sequence integrity. High speed switching. Cell header processing. –VPI/VCI translation

5 Copyright © Monash University Switch types Workgroup switches Campus switches Core switches

6 Copyright © Monash University Types of Switching Backplane Blocking –Routing Conflicts –Cells are lost if no internal buffers. –Cells are stored in a queue if there are internal buffers. Non-blocking –No internal blocking. –Buffers at the inputs and/or outputs.

7 Copyright © Monash University ATM Switch Architectures Crossbar –Most campus switches Multiple Bus –Most workgroup switches Multistage –Most core switches

8 Copyright © Monash University Best performance Very expensive for large switches Cost increases as where NXN is the switch size. Crossbar

9 Copyright © Monash University Multiple Bus Lowest cost Poor scalability Poor performance due to bus contention Inputs Outputs Busses

10 Copyright © Monash University Multistage Switches Interconnection of a number of crossbar switching elements. Single path or multiple path. Buffers required to store packets. Very cost effective. Highly scalable.

11 Copyright © Monash University Multistage Switching Fabric

12 Copyright © Monash University Routing in Multistage Switches Self routing using destination tags Internal routing conflicts may –reduce the throughput, –increase the delay and –increase the cell loss in a switch.

13 Copyright © Monash University Self-Routing Principle VPI/VCI translation only at the input of the switching network Cell extended by a switching network internal header Cell header extension requires increased internal speed. Suitable for large multistage networks

14 Copyright © Monash University Self-routing (contd.)

15 Copyright © Monash University Self Routing: Example

16 Copyright © Monash University Multicast with Self-Routing

17 Copyright © Monash University Tree Saturation Hot spot traffic – A lot of traffic may be directed to a particular output. Tree saturation reduces the performance of the switch Saturated tree blocks traffic to other (non hot) outputs as well.

18 Copyright © Monash University Contention in a Multi-stage Switch

19 Copyright © Monash University Batcher-Banyan Switch A Banyan network has no internal conflict if cells are arranged in ascending or descending order of output destination. A Batcher network is used to sort cells in ascending order.

20 Copyright © Monash University Batcher-Banyan (contd.)

21 Copyright © Monash University Table-controlled VPI/VCI translation VPI/VCI translation at each switching element. Cell length need not be altered. Table contents are updated during connection set-up.

22 Copyright © Monash University Table-controlled (contd.)

23 Copyright © Monash University Buffering in Switches Buffers store the cells that lose routing conflicts. Location of buffers: –Internally, Externally –Input, Output, Shared, Crosspoint

24 Copyright © Monash University Input Buffered Switch

25 Copyright © Monash University Input Buffers Head of line blocking reduces throughput Inefficient utilisation of buffer space Simple buffer management

26 Copyright © Monash University Head-of-Line Blocking

27 Copyright © Monash University Output Buffered Switch

28 Copyright © Monash University Output Buffers No head of line blocking Inefficient utilisation of buffer space Requires expensive high speed buffers

29 Copyright © Monash University Shared Buffer

30 Copyright © Monash University Shared Buffer High buffer utilisation. Needs least amount of buffer space. Buffer hogging with non uniform traffic. Complex buffer management strategy. Needs expensive high speed buffers.

31 Copyright © Monash University Crosspoint Buffer

32 Copyright © Monash University Crosspoint Buffer Combines the advantages of input and output buffers Inefficient utilisation of buffer space Simple buffer management

33 Copyright © Monash University Buffer Size Requirements Buffer sizes for average load of 85% at each input and a permissible cell loss probability of 10 -9

34 Copyright © Monash University Buffer Management Queuing –How to organise buffered cells Scheduling –When and in what order to service queues

35 Copyright © Monash University Buffer Management Which cell to transmit next? Arbitration strategies based on –Random –fairness –minimise cell loss –minimise cell delay variation

36 Copyright © Monash University Arbitration Strategies State dependent: –Longest queue served first –Lengths of buffers have to be compared Delay dependent: –Queue having the maximum delay served first –Overhead in storing order of arrival information

37 Copyright © Monash University Buffer Queuing Policies First in - First out (FIFO) Strict Priority Fair Queueing (Per VC queueing) Weighted Round Robin Weighted Fair Queuing

38 Copyright © Monash University Performance Measures Throughput: Number of cells switched per unit time. Cell loss probability: Loss from routing conflicts or insufficient capacity Cell delay: Delay inside switch. –Switching delay: fixed –Queueing delay: variable –jitter: Cell delay variation.

39 Copyright © Monash University Conclusion –Switching terms and requirements –Switch architectures –Multistage switches self routing Batcher-Banyan switch –Buffering schemes Input, output, shared, crosspoint –Output buffer management –Performance measures

40 Copyright © Monash University Questions An ATM switch is functioning normally, until a video server and video client are connected to it. When the video is played back from the server through the switch, other (low bandwidth) applications using the switch fail. The video delivered is jerky. What are some possible explanations for this?