1. Switch Performance Analysis and Design Improvements
IEG4020
Telecommunication Switching and Network Systems
Chapter 4
Switch Performance Analysis and Design Improvements

2. Internally Nonblocking Switch: Loss System1 2 3
Pr[ carry a packet ] = 0
P = Pr[ carry a packet ]
for large N
For 0 =1, p  0.632

3. Fig. 4.1. Illustration of head-of-line (HOL) blocking.2 3 4
Outputs
Internally Nonblocking Switch
Losing packet
Winning packet
Input Queues
Cannot access output 2 because it is blocked by the first packet
Fig Illustration of head-of-line (HOL) blocking.

4. Internally Nonblocking Switch1 2 3 4
Outputs
Internally Nonblocking Switch
(input, output)
Fictitious Output Queues formed by HOL packets
(1,2)
(1,1)
(2,3)
(2,1)
(3,2)
(4,4)
(4,1)
Output 4
Output 3
Output 2
Output 1
Fig An input-buffered switch with the fictitious queues used for analysis.

5. Throughout of Input-Buffered Switch
Consider a fictitious queue associated with a particular output i
= # packets at start of time slot m.
= # packets arriving at start of time slot m.
= # packets remaining at end of time slot m
= # inputs that won contention in time slot m

6. i 1 2 3
time slot m
time slot m-1
e.g. Fictitious Queue i

7. The empty probability of any output link is… …

8. is Poisson and independent of as N  

9. under saturation
max. throughput

10. Meaning of Saturation Throughput
Input Queue
Let be the saturation throughput of the input-buffered switch with FIFO discipline.
When the offered load , the throughput , the system is stable.
When the offered load , the throughput , the system is saturated. In this case, with probability 1 the buffer will overflow.

11. How about small N?
Table Maximum throughput for input-buffered switches of different sizes.

12. Service times at different fictitious queues are independent
Output 1
Fictitious Queues
Output 2
Output N
Input Queue
Time spent in HOL are independent for successive packets when N is large
Service times at different fictitious queues are independent 2 N
HOL
1/N
Fig Queuing scenario for the delay analysis of the input-buffered switch.

13.  X0 
 X3
X2
 X 
 X0 
Busy period
Idle period Y t
U(t)
Arrivals here are considered as arrivals in intervals i-2
Arrivals here are considered as arrivals in intervals i-1
Xi-1 Xi
Fig The busy periods and interpretations for delay analysis of an input queue.

14. mi =2 prior arrivals
Arrival of the packet of focus. One simultaneous arrival to be served before the packet; L=1.
Departure of packet of focus. Xi
Xi+1 Ri W
-- Packet arrival in interval i.
-- packet departure in interval i+1.
-- number of arrivals
(n)
(1)
(2)
Fig Illustration of the meanings of random variables used in the delay analysis of an input queue.

15. 0
Fig Different contention-resolution policies have different waiting time versus load relationships, but a common maximum load at which waiting time goes to infinity.

16. t 1
Simultaneous arrivals are randomly placed on a unit line to determine the order of service
Packet whose waiting time is being analyzed is placed at t
Fig A unit line for determining the order of service among simultaneously arriving packets.

17. Queuing Analysis in Output-buffered Switch
Switch with Speedup factor of N.
Arriving packets reach the targeted output ”immediately”.
= # arriving packets at start of time slot m 1
 = load
as N  
Poisson Distribution.

18. Delay in Output-Buffered Switch
not necessarily  1
Little’s’ Law
Average Delay

19. What if FIFO constraint removed ?
Look-ahead scheme : look at first  packets at each queue.
cost
 = overhead of one round of contention
Actual throughout =  * 1
0.59 2
0.70 3
0.76 4
0.80 

20. Fig. 4.8. The speedup principle.
Switch with speedup factor = S
To avoid packet loss at inputs, input queues are needed if S < N
Output queues are needed because packets may arrive too many at a time for immediate transmission at outputs
Each switch cycle = 1/S time slot. Up to S packets may leave a given input or reach a given output in a time slot.
Fig The speedup principle.

21. 2 1
Packet 2 will be directed to switch 2 if packet 1 is cleared in switch 1. Otherwise, packet 1 will be directed to switch 2.
Packet 2
Packet 1
Packets are directed to switch 1 in the first half-time slot and to switch 2 in the second half-time slot.
Fig (a)

22. 2 1
(b)
Output address
Packet cut into half
Packet assembled
Fig Methods for achieving speedup effect without speeding up switch operation: (a) using multiple switches; (b) using packet-slicing concept.

23. Channel Grouping N x NR N 1 R
In each time slot, at most 1 packet from each input and up to R packets to each output are cleared. * 2 3 4
0.59
0.89
0.98
 1
Fig Channel Grouping

24. 1 2 3 4
e.g. R=S=2
All packets cleared if speedup; packet 3 not cleared if channel grouping

25. Banyan Network 0
Banyan Network R-1
R-2
Batcher Network
MUX
Output 0
N-1
Output i (i=0, …, N-1) connected to input  i/R  of banyan network i mod R.
Fig A Batcher-R-banyan network that implements the channel- grouping principle.

26. R
Truncated Banyan Network 1 N
R-1
Fig (a)

27. Truncated Banyan Network
b1b2…bR R
Relative output 00 …0
Relative output bR+1 …bn
Relative output 11 …1
Inputs connected to outputs b1 ...bR of all expanders
(b)
Fig (a) The expansion banyan network; (b) Labeling of the truncated banyan network and its output groups.

28. Shifting Concentrator
mux
Output Queue
Rx1 switch working at R = 4 times the links rate 1 R
(a)
Shifting Concentrator 1 R
mux
Rx1 switch working at same speed as link rate
Packets are loaded into queues in round-robin fashion
Packets are read out from queues in round-robin fashion
(b)
Fig (a) Multiplexer and output queue at an output of a channel-grouped switch. To accommodate simultaneous packet arrivals, the multiplexer must work R times faster than link rate. (b) An implementation of a logical FIFO queue such that the multiplexer only have to work at same speed as link rate.

29. Max Throughput of Channel-grouped switch
zis are roots of numerator
can show the roots of denominator zR-A(z) are 1, z1, z2  …, zR-1  where |zi  | < 1
zi = zi  i, Otherwise C(zi ) infinity which is not possible

30. Knockout Principle
If R is large, (e.g. R = 8), might as well not queue packets at inputs. Simply drop them.
Loss probability is small

31. Loss Probability in Knockout Switch

32. We can show that the loss probability is bounded by
By employing the following inequalities
(1)
(2)

33. Proof of

34. Proof of
By the Taylor series expansion

35. (by letting i = k - R )
by applying (1)
Mean value of binomial random variable ρ/ N

36. By applying (2)
(independent of input loads)
(independent of ports)

37. Fig 4.14. A Batcher-banyan knockout switch.? = 1
N-1 R
Batcher Network
Reverse-banyan Concentrator
R+1
NxN banyan (1)
NxN banyan (2)
NxN banyan (R)
MUX a b
Packet 1
Packet 2
Output Address
Let packet 2 go through if and only if ab
Fig A Batcher-banyan knockout switch.

38. Fig. 4.15. Running adder network.
Running Adder Network (RAN)
produces concentrator - output address 1 2
RAN
Fig Running adder network.

39. Central Controller
Reverse banyan Concentrator
(a) +
Address assigned=Sum of all activity bits above
Running Sum
Info b b
Info a a
a+b
(b)
Packet B
Packet A
Fig (a) A central controller for computing the assignments of packets to concentrator outputs; (b) a running-adder address generator that computes the assignments in a parallel and distributed manner.

40. Knockout Concentrator
Shifter 1 2 R
Output 1 N
Input
Output
Output N
Fig A knockout switch based on broadcast buses and knockout concentrators.

41. Losing packets D
Packet filters
Input
Knockout element
Delay element 1 2 3 4
Output
Number of switch elements = (N-1)+(N-2)+ … (N-R) = NR-R(R+1)/2  NR

42. Packet a
Packet b
Inactive
Fig An 8x4 knockout concentrator and operation of its component 2x2 switch elements.

43. Replication Principle
Single Banyan Network :
Random Routing Parallel Banyan :
For a fixed Ploss requirement,
so, order of complexity = Nlog2N with a large constant.

44. Fig. 4.19. A parallel-banyan network.
1st Banyan Network
Kth Banyan Network 1 2 N
Random router or broadcaster
Statistical multiplexer
Fig A parallel-banyan network.

45. Fig. 4.20. An 8x8 banyan network with dilation degree 2.
010
001
100
011
000
111
110
101
Fig An 8x8 banyan network with dilation degree 2.

46. 2 dxd concentrator Complexity~ O(dlogd)
Fig An implementation of 2dx2d switch element with order of complexity dlogd.
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