Susanta K Pal Variable Energy Cyclotron Centre 1/AF, Bidhan Nagar, Kolkata – , India MUCH Electronics: Indian Effort Physics with FAIR: Indian Perspective March 8 to 10, March Physics With FAIR: Indian Perspective, Susanta K Pal

Introduction : PMD from SPS to RHIC and LHC Electronics and Readout for STAR FEE Development TRIGGER DAQ Electronics and Readout for ALICE FEE Development TRIGGER LV Distribution MUCH Electronics: Understanding of Electronics FEE RORC INDIAN Contribution to CBM MUCH Electronics Remarks 10 March Physics With FAIR: Indian Perspective, Susanta K Pal MUCH Electronics: Indian Effort

At SPS (WA93/WA98 Experiments) Scintillator pads with wavelength shifting fibres using image intensifier + CCD camera systems readout. 3 X0 thick Lead converter Scintillator pads of size: 10, 15, 20, 25 mm 2 WA93 ( ) : 8000 pads covering 3m 2 WA98 ( ): pads covering 21m 2 At RHIC and LHC (STAR and ALICE experiments) Honeycomb gas proportional counter with copper honeycomb cathode, gold plated tungsten wire anode, anode signal processing using GASSIPLEX and MANAS, 3X0 thick lead converter. STAR : 83,000 cells, 1 sq.cm cross-section, 8mm gas depth. Installed in 2002 and data taking is going on ALICE : 220,000 cells, 0.22 sq.cm cross-section, 5mm gas depth. Installed in 2008 and data taking is going on PMD probes thermalisation (flow), phase transition (multiplicity fluctuation), Chiral symmetry restoration (charged-neutral fluctuation ) Introduction: Preshower Photon Multiplicity Detector (PMD) SPS  RHIC  LHC  CBM 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

WA98 PMD pads, 21 sq.m. area 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

STAR (Identical with ALICE PMD TDR design) Preshower Detector with fine granularity Two planes: Veto + Pre-shower  Coverage: 2.3 – 3.9 Total no. of cells: 82,944 Distance from vertex: 550cm Cell cross section: 1.0 cm 2, depth: 0.8 cm Readout: GASSIPLEX C- RAMS 24 Supermodules, 144 Unit modules Rhombus geometry of unit modules PMD front view Joining of two halves 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

FEE board With 4-Gas Chips Copper honeycomb Bottom PCB Top PCB Basic design of PMD 70-pin connector 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

DETECTOR GAS-4 BOARDS FEE BUFFER CRAMS TRANSLATOR SEQUENCER Detector signals processed by GASSIPLEX (16 channel Analog Signal Processor ) chips. Entire Readout consists of 48 chains for channels. Each Chain consists of :  Translator ( NIM to V Levels) for control Signals  27 No. Gas-4 Boards (1728 channels)  Buffer to carry Analog Mux Signal to Digitizer(CRAMS,SEQ) Clear, CLK T/HOLD BLOCK DIAGRAM for READOUT SCHEME at STAR 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

Technology : Alcatel-Mietec-0.7  m Silicon area : 3.63 x 4 = 14.5 mm 2 Peaking time1.2  s Peaking time adjust.1.1 to 1.3  s Noise at 0 pF 530 e - rms Noise slope11.2 e - rms/pF Dynamic range ( + )560 fC (0 to 2 V) Dynamic range ( - )300 fC (0 to –1.1 V) Gain3.6 mV/fC Non linearity  2 fC Baseline recovery .5% after 5  s Analog readout speed10MHz (50 pF load) Power consumption8mW/chan. at 10 MHz Output Temp Coeff.0.05 mV/ 0 C SPECIFICATIONS BLOCK DIAGRAM OF GASSIPLEX 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

BufferTranslator Gas-4(M)Gas-4(N) Protection Board PCB LAYOUTS : GAS -4 Boards 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

80 Translator boards fabricated and tested at VECC 80 Buffer boards fabricated tested at VECC 8 –10 % Gas-4 Boards were found to be faulty after assembly GAS-4 boards assembled at KHMD BANGALORE 3000 Protection Boards assembled and tested at VECC 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

C-RAM Sequencer CRAMS Translator,Gas-4 board, Buffer Pedestal for 1728 channels 10 March

VME NIM RACK-1 CPU Sequence r CRAMS CPU Sequence r CRAMS CPU Ethernet SW DAQ Room Experimental Site PMD01 PMD02 PMD03 VME Crate-1 VME Crate-2 PMD DAQ SETUP at STAR Arrangement of C-RAMS 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

Most Crucial Challenges faced : To Design the Trigger Logic - L0 of STAR is after 1 us -Peaking time of Gassiplex is 1.2 us Solution: - Use PreTrigger form ZDC of BBC with L0 - Separate Trigger Logic for PMD was designed in tune with STAR main Trigger 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

PMD TRIGGER STAR Experiment 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

STAR PMD running since January, March Physics With FAIR: Indian Perspective, Susanta K Pal Photon Multiplicity Detector (PMD) in STAR

PMD PMD in LHC 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

PMD in ALICE ,  coverage , 2  Distance from IP361.5 cm Cell cross-section0.22 cm 2 Cell depth0.5 cm No. of UMs48 No. of cells in a UM4608 No. of HV channels48 Signal processingMANAS Total Cells March Physics With FAIR: Indian Perspective, Susanta K Pal

Electronics Architecture for PMD in ALICE 3 Level hierarchy - Integrated preamplifiers (16 channels per chip) MANAS –Embedded read-out daugther board with coding and zero suppression (64 channels) MANU + MARC (digital asic) –Concentrator and processing board CROCUS 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

FEE Features –64 cell inputs –Embedded on the chambers –On-board analog to digital conversion 12 bit / 32 µs for 64 channels –Digital communication with upper level 20 Mbyte/s –Zero suppression MANAS MARC DETECTORDETECTOR MANAS T/H CLR CLK-1 CLK-2 Analog Out ADC 0 ADC 1 CS CLK-ADC 12 Bit ADC AD 7476 KM 4110 KM 4110 MARC CAL TOKEN-IN TOKEN-OUT CONTROL SIGNALS DIGITAL BUS-LVTTL DATA SIGNALS, LPCLK LINK PORT Main Components: 1.MANAS (Multiplexed-Analog-Signal-Processor ) 2. MARC ( Muon-Arm-Readout-Chip ) 3. ADC (Analog to Digital Converter ) 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

Timing sequence of the control signals for the MANAS-16 multiplexed readout. MARC block diagram. 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

FEE Board-Top side FEE-Board (Bottom side) LVDS LVTTL Translator Bridge Board (Digital buffer) Readout Boards Using MANAS ( 4-Chips: 64 Channels) 4000 Boads 6 layer, Size 70*24 m 1 mm thick PCB 4 layer boards- Size 63*36 mm 1mm thick PCB 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

UM-long FEE LV Flexible link BB TB Patch Cable LVTT L bus 12 boards on UM, Back plane PCB Vertical Mounting of Boards 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

Concentrator board : FPGA TRIGGER FPGA SIU Interface SIU INTERFACE BOARD Debug Trigger & config DDL to RORC JTAGJTAG JTAGJTAG Front board JTAGJTAG JTAGJTAG JTAGJTAG JTAGJTAG JTAGJTAG JTAGJTAG JTAGJTAG JTAGJTAG JTAGJTAG JTAGJTAG CROCUS Structure DSP Analog Device BGA 400 Pins at 80Mhz EEPROM TO VME DISPATCHING TO 10 PATCH BUS Front board : UP TO 10 PATCH connected via linkport and serial port 2 DSPs analog Devices From 1 to 5 front boards 2 DSPs analog Devices, driving the front board 2 DSPs for the event building, the monitoring, the debug. 1 FPGA for the trigger and board control 1 FPGA to make the interface with the SIU 1 SIU interface board 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

Translator Patch Bus 2 *32 cells TRIGGER L0 BUSY LTUCTP VME TRIGGER DISPATCHING 40 meters LVDS LINKPORTS TRIGGER BUSY, and L0 DDL LDC GDC CROCUS CHAIN Total no of cells : Total no of Modules : 48 1 module = 4608 cells. 1 CROCUS - 50 Patch Buses 6 CROCUS – 300 Patch Buses Connection of a Chain 8.5 mt 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

ALICE LV Distribution Chain 1 Chain 2 Chain 3 Chain 4 Chain 5 Chain 6 LV In V supply Filter-Box3-phase supply With sense Wire EASY 3000 A3009B LVDB One detector module = (72 FEE) i.e. 6 chains with 12 FEE boards per chain ALICE-FEE having 6chains in a module DC-DC Converter +2.5V -2.5V +3.3V

DAQ-ARCHITECTURE 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

Timing of the acquisition Sequence 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

Contribution to STAR and ALICE PMD with Full Electronics Readout Concentrator Board Integration of PMD DAQ with main STAR and ALICE DAQ EPICS based Detector control system at STAR PVSS based Detector Control System integrated with main ALICE DCS Tier2 for LHC Grid for processing large volume of data Next, FOR MUCH Electronics at CBM Experiment 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

measure: π, K measure: K, , , ,  measure: D 0, D ±, D s,  c measure: J/ ,  '  e + e - or μ + μ - measure: , ,   e + e - or μ + μ - measure: γ Hadrons Leptons Photons trigger<10 AGeV trigger trigger e + e - offline offline>10 AGeV offline ? offline for e + e - trigger for μ + μ - ? assume archive rate: few GB/sec 20 kevents/sec trigger on high p t e + - e - pair trigger on displaced vertex drives FEE/DAQ architecture trigger μ + μ - μ identification Data Acquisition at CBM(FAIR) From Walter F.J. Mueller’s lecture 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

Conventional FEE-DAQ-Trigger Layout in HEP Detector Cave Shack FEE Buffer L2 Trigger L1 Trigger DAQ L1 Accept L0 Trigger f bunch Archive Trigger Primitives Especially instrumented detectors Dedicated connections Specialized trigger hardware Limited capacity Limited L1 trigger latency Modest bandwidth From Walter F.J. Mueller’s lecture 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

Limits of Conventional Architecture Decision time for first level trigger limited. typ. max. latency 4 μs for LHC Only especially instrumented detectors can contribute to first level trigger Large variety of very specific trigger hardware Not suitable for complex global triggers like secondary vertex search Limits future trigger development High development cost 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

Typical Self-Triggered Front-End Average 10 MHz interaction rate Not periodic like in collider On average 100 ns event spacing time amplitude a: 126 t: 5.6 a: 114 t: 22.2 Use sampling ADC on each detector channel running with appropriate clock Time is determined to a fraction of the sampling period threshold From Walter F.J. Mueller’s lecture 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

L1 Select High bandwidth The way out.. use Data Push Architecture Detector Cave Shack FEE DAQ Archive f clock L2 Select Self-triggered front-end Autonomous hit detection No dedicated trigger connectivity All detectors can contribute to L1 Large buffer depth available System is throughput-limited and not latency-limited Use term: Event Selection Buffer 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

Front-End for Data Push Architecture Each channel detects autonomously all hits An absolute time stamp, precise to a fraction of the sampling period, is associated with each hit All hits are shipped to the next layer (usually concentrators) Association of hits with events done later using time correlation Typical Parameters: – with few 1% occupancy and 10 7 interaction rate: some 100 kHz channel hit rate few MByte/sec per channel whole CBM detector: 1 Tbyte/sec 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

Read-out ASIC to be used for MuCh is n-XYTER / CBM-XYTER  mixed signal chip  process: AMS 0.35 μm CMOS  128 channels  1 test channel with analogue diagnostic output  architecture for AC-coupling, employable for positive and negative signals  self triggered, data driven de-randomizing, sparcifying readout at 32 MHz  digital time stamp output  analogue peak hight output  maximum data loss at 32 MHz average input rate over 16 μs: 4%  analogue pile-up registry Key Features 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

 programmable dead time  local threshold adjustment  Dynamic Range: e  Shaping time and noise performance:  30 ns fast shaper at 30 pF input, 850 enc for positive signals, 1000 enc for negative signals  130 ns slow shaper at 30 pF input, 600 enc  Timing resolution ~ 2-3 ns, time stamp resolution 1 ns Key Features contd.. 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

MuCh Electronics Perspective Main Issues : – Detector PCB design – FEE Board Design – LV distribution to FEEs – HV distribution to Detectors – Connectivity and Placement ROC Boards – Cooling design 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

Basic n-XYTER Readout Chain Detector FEBROC XYT E R ADC XYT E R Tag data ADC data clock FPGA control SFP MG T DCB FPGA SFP MG T Front-End Board Read-Out Controller Data Combiner Board to other ROC's to ABB SFP MG T From Walter F.J. Mueller’s lecture 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

For next Test beam Top copper Pad area- 67*73 Sq mm For 3mm. For 4mm - 88*97 sq mm Detector PCB design  Main Features :  Both 3 and 4mm square pad sizes  Not Staggered (‘09 test beam module)  Symmetric Square Pads  Multi Layers ( 4) with GND Planes  Signal Tracks are distributed in 3 planes Reduce the capacitance Track to Track spacing increases Reduce Cross talk  Blind Vias for gas integrity  Gnd Tracks between Signal Tracks Bottom copper Connector with resistors Top copper GND Plane Bottom copper GND Plane Connectors for FEBs Inner 1 Inner 2 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

Slat Type 2m  20 Chambers  Width of each chamber 10 cm. X-section of chamber  Chambers layout for MuCh  Profile is less as compared to Square type (30cmX30cm) design  Some Wastage of chamber space Detector PCB design Let us proceed with some conceptual Modular Design with Slat Type 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

Inner 1Inner-2Bottom Copper Top copper Blind vias from inner layers( blue) Blind vias (red ) to inner layer 2.6 mm square pads  Pads arranged in one block of 32*8=256.  Connected to 300 pin connector.  Tracks - shorter and not closer.  can be easily duplicated for bigger sizes.  40 such FEE Boards for One Slat of 1mt. Length..  Each block read by 1 FEB with 2/4 n-XYTERs ( 128/64 Channels)  FEBs can be mounted horizontal or vertical  Modular Approach Detector PCB design 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

10 March 2010 Physics With FAIR: Indian Perspective, Susanta K Pal 42 BLOCK DIAGRAM OF FEE BOARD Wire Bonding Scheme Representative Diagram WIRE BONDING 3D VIEW COMPLEX PART OF FEE BOARD GERBER VIEW Prototyping 3 CM X 3 CM Small PCB made at VEC It has been found that the most of the pads are not suitable for bonding Front-End Electronics Board (FEE) – PCB for Wire Bonding We are discussing with PCB manufacturrer very actively for 256 channels FEE board with our design which involves wirebonding and PCB fabrication to accommodate 50 micron pitch effectively We can also check fabrication capability of FEE board with the new design by GSI Gerber file It is observed that it will help us if the XYTER ASIC is a packaged chip Crtical part of FEE Prototype Developmnt

FEB--Probable scheme?? 64 channel chip-- No of Pin outs ? For inputs- 64 For I2c - 6 For CLK - 6 For SDA, SCl - 2 I2C Reset - 2 Reset 2 DATA (diffl) ( 16 for digital, 2 analog) Total -100 PLUS Bias,GND, other control inputs -25 to 50 ?? Considering BGA144(1,27mm pitch) / SQFP148(10*14) ??? with 148 pin count and if we arrange-see the board size-10cm*3.2cm BGA-144 ADC 300 Pin CON SQFP148 ADC ROC CON 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

Block Diagram of ROC Board  Two nos. of such Boards are already fabricated in India  Functional testing is in progress Diagram taken from CBM-Wiki page 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

Gas out Conceptual sketch of Triple GEM chamber module Gas in Segmented LV power line/power plane on Detector PCB  each power line is feeding 5-FEBs  ground plane of LV line is in other layer of PCB HV 1 mt 10cm To be decided LV connector 40 FEBs in one module in 1mt slat with about channels 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

FEBs-LV Channels to be read= 500,000 One N-XYTER reads =128 channels. FEB with 2 n-XYTERS reads-256 channels No of FEB s Required = 500,000÷256 = 2000 No (512,000 channels). Each ROC can handle = 2 FEBs (512 channels). No Of ROCs required =1000Nos. LV Specifications 2chip Feb With 3.3 v supply the power dissipation =10watts FEBs consume =2000x 10Watts =20KW. One ROC need ( one FEB connected). With two FEBs it is 4A 1000 ROC s consume = 1000x5Vx4A=20KW. Power consumption expected for 2000FEBs ROCs = 40KW 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

CAEN A3009B -2to 8 V, Max =45W. Has 12 independent channels. Max 480Watts For 1000 ROCS Need 1000÷12= 84 modules For 2000 FEBSs = 2000÷12= 167 modules. Need =251 modules. Separate LV channels for FEB and ROC. Alternative: Reduce LV channels to 168÷2=84 by using LVDB to feed 2 FEBS (from 1 channel) Need =168 modules. No of 3009s in one EASY crate =4 (2KW) CAEN EASY crates Required = 250÷4=63 or 164 ÷4=41 With 2 channels 3486 has =48V /40A, Power Capacity =5KW 3486 s required = 40KW÷5 = 8Nos. Filter for 3486 =8 Nos One Branch Controller (A1676A) controls 6 EASY Crates. For 63/41 Crates we need = 11 /7 Branch controllers LV distribution : some preliminary thoughts 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

Connectivity Between FEB and ROC Radiation dose ROC boards may be affected by this radiation environment Plan to put the ROC boards 3mt apart from the 0-axis Detail dose calculation is needed at that point (seems to be falling fast) The breakdown value of TID is also to be investigated for ROC components Cable Type Length of the cable to be known for error free communication Shielded twisted pair flat type may be a good choice TID: Total Ionizing Dose at the outer edged of the detector is around 10krad Ref : 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

Tracking station plane 2m ROC stack 3mt (approx) Placement of ROC Boards ROC stack 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

FEE Board Infra Structure Board Optical Link to ROC Some thoughts : Transmitting data through Optical Link FEE Board Infra Structure Board Optical Link to ROC

Forced air cooling for FEE Cool air input duct (above dew point) Hot air Extraction duct Air-tight enclosure 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

Indian Contribution to CBM MUCH Electronics India could supply complete electronics for MUCH XYTER integration for 0.5x10 6 detector channels: -two chips (256 channels) to one hybrid FEE PCB (estimated 2000 boards) FPGA-based readout controller (ROC) -adaptation and assembly ( ~500 boards needed) For a test case 2 ROC boards of current version have already been fabricated in India 10 March Physics With FAIR: Indian Perspective, Susanta K Pal

Remarks : Some Preliminary thoughts has been put for the design of  Detector PCB : Here we need the following for the final design  Type of Module ( Square or Slat or Sector) and its size  Pad size  FEE PCB : Here we need the following for the final design  Type of package of XYTER chip (??)  No. of channels in one XYTER chip ( 64 or 128 or 32??)  Gap between chamber and absorber i.e maximum available profile for FEB for mounting ( Horizontal/Vertical)  Placement of ROC :  Radiation dose near to the Detector.  Detector Control System:  EPICS or PVSS will be used for controlling/monitoring LV/HV/Temperature etc.(?)  We need to finalise the LV/HV Modules  Selection of HV/LV and Cooling  If radiation environment permits (at 3mt distance), we propose to use TRD electronics for MUCH as well. 10 March Physics With FAIR: Indian Perspective, Susanta K Pal