CS-EE 481 Spring University of Portland School of Engineering Project Golden Mantle CMOS 8-Bit Analog-to-Digital Converter Team T Travis Tompkins K Aaron Krizek O Scott Ostrow Advisor Dr. Joe Hoffbeck Dr. Peter Osterberg Industry Representative Mr. Howard Voorheis

CS-EE 481 Spring University of Portland School of Engineering Overview Introduction Accomplishments Plans Issues/Concerns Demo Conclusions

CS-EE 481 Spring University of Portland School of Engineering Introduction 8-Bit Analog-to-Digital Converter “Tracking” ADC Architecture

CS-EE 481 Spring University of Portland School of Engineering Introduction continued Continuous time signal “coded” into stream of binary numbers Key component in communication systems - Cell Phones, Satellite Transmission, Digital Signal Processing

CS-EE 481 Spring University of Portland School of Engineering Accomplishments Theory of Operations and Approval Meeting Layout determined Solved CMOS/Macro Model cross connection problem Core Components of Macro Model tested Tracked AC and DC signals

CS-EE 481 Spring University of Portland School of Engineering Pictures

CS-EE 481 Spring University of Portland School of Engineering MOSIS CHIP Bonding pads: 40 Layout size: 2200 x 2200 microns; Area: sq mm Packaging: DIP40 Maximum die size: 7366 x 7366

CS-EE 481 Spring University of Portland School of Engineering Bill of Materials

CS-EE 481 Spring University of Portland School of Engineering Plans Individual Component Testing Prototype Integration Begin Wire-Wrap Phase Develop Logic to Prevent Looping in Macro Model

CS-EE 481 Spring University of Portland School of Engineering Milestone Table NumberDescriptionOriginalPreviousPresent 1Product Pre-Approval09/08/04 2Functional Spec Approval v1.0 (Approval Meeting) 10/08/04 10/11/04 3Project Plan Approval v1.0 (Approval Meeting) 11/05/0411/08/04 6*.tpr File Completion11/24/04 7Off-chip Components Ordered12/03/04 8Design Release (Approval Meeting) 12/06/04 12/15/04 9TOP’s Approval v1.0 (Approval Meeting) 02/11/05 10Chip Received From MOSIS03/15/05* 11Prototype Release04/08/05 12Founder’s Day Presentation04/12/05 13Final Report04/22/05

CS-EE 481 Spring University of Portland School of Engineering Concerns/Issues Timing Violations Wire Wrap Techniques Arrival of CMOS chip Logic to prevent looping in Macro Model

CS-EE 481 Spring University of Portland School of Engineering Detail: Timing Violation Solution

CS-EE 481 Spring University of Portland School of Engineering Demo Tracking Demo

CS-EE 481 Spring University of Portland School of Engineering Conclusions Introduction Accomplishments Plans Issues/Concerns Demo