ENG241/ Lab #41 ENG2410 Digital Design LAB #4 Design of Combinational Logic “The Trip Genie”

Slides:



Advertisements
Similar presentations
Give qualifications of instructors: DAP
Advertisements

CS 151 Digital Systems Design Lecture 37 Register Transfer Level
08/07/041 CSE-221 Digital Logic Design (DLD) Lecture-8:
Digilent Spartan 3 Board Discussion D3.3
EET 1131 Unit 4 Programmable Logic Devices  Read Kleitz, Chapter 4.  Homework #4 and Lab #4 due next week.  Quiz next week.
EE/CS 120A Lab 4 LAB 3 report due on this Friday 2:00pm.
Combinational Logic Design
ECE 448: Spring 12 Lab 4 – Part 2 Finite State Machines Basys2 FPGA Board.
CPE 169 Digital Design Laboratory Digilent Inc. Nexys Development Board.
Introduction to Digital Design Lab Project
EEL-3705 Digital Logic Design Spring 2006 Semester Professor R.J. Perry.
Figure 5–1 An example of AND-OR logic. Open file F05-01 to verify the operation. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education,
Digital Logic Lecture 08 By Amr Al-Awamry. Combinational Logic 1 A combinational circuit consists of an interconnection of logic gates. Combinational.
Chapter 4 Programmable Logic Devices: CPLDs with VHDL Design Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights.
Advanced Digital Circuits ECET 146 Week 3 Professor Iskandar Hack ET 221B,
Experiment #3A: Introduction to Function Reduction, Function Forms, and VHDL Implementation CPE 169 Digital Design Laboratory.
Adders and Multipliers Review. ARITHMETIC CIRCUITS Is a combinational circuit that performs arithmetic operations, e.g. –Addition –Subtraction –Multiplication.
LAB 9 Finite State Machine (FSM) Ui Luu Glendale Community College Bassam Matar Chandler-Gilbert Community College.
Combinational Logic Design CS341 Digital Logic and Computer Organization F2003.
Comments on Lab #4 Annotating Timing Diagrams Draw viewer’s attention to the points you are trying to show / verify –Important output states glitch or.
Advanced Digital Circuits ECET 146 Week 4 Professor Iskandar Hack ET 221G,
Lab 0: Groups and Equipment Start date: Week #2 Due date: no report 1.
1 Combinational Logic Design Digital Computer Logic Kashif Bashir
ENG2410 Digital Design LAB #8 LAB #8 Data Path Design.
LAB #2 Xilinix ISE Foundation Tools Schematic Capture “A Tutorial”
Combinational Building Blocks: Encoders and Decoders Experiment 6.
ENG2410 Digital Design LAB #6 LAB #6 Sequential Logic Design (Flip Flops)
ENG2410 Digital Design LAB #5 Modular Design and Hierarchy using VHDL.
Lab 2 : Overview Combinational System.
displayCtrlr Specification
CascadedBCDCntr&Display Aim : Capture, simulate and implement a 2-digit, loadable BCD up/down counter, with chip enable I/P (CE) and chip enable O/P (CEO).
Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. Slide 1 Digital Fundamentals.
 Seattle Pacific University EE Logic System DesignAlteraBoard-2 Altera Cyclone II (484 Pin BGA) 22 Pins.
Digital Logic Circuits. Overview Objectives Background Materials Procedure Report/Presentation Closing.
ENG241/ Lab #11 ENG2410 Digital Design LAB #1 Introduction Combinational Logic Design.
FPGA CAD 10-MAR-2003.
ENG2410 Digital Design LAB #7 LAB #7 Sequential Logic Design “Sequence Recognizer” Using both Schematic Capture and VHDL.
Chapter 0 – Week 2 Combinational Logic Design. What have been discussed Design hierarchy –Top – down –Bottom – up CAD HDL Logic synthesis.
Department of Electronic & Electrical Engineering Combination Lock. Plan. Demo. Brief Report. Code.
Introduction to LabVIEW
ECE 448 Lab 3 FPGA Design Flow Based on Xilinx ISE and ISim. Using Seven-Segment Displays, Buttons, and Switches.
FIGURES FOR CHAPTER 16 SEQUENTIAL CIRCUIT DESIGN
Copyright © 2007 by Pearson Education 1 UNIT 6A COMBINATIONAL CIRCUIT DESIGN WITH VHDL by Gregory L. Moss Click hyperlink below to select: Tutorial for.
Circuit Synthesis A logic function can be represented in several different forms:  Truth table representation  Boolean equation  Circuit schematic 
Lecture 1 Gunjeet kaur Dronacharya group of institutions.
LAB #5 Modular Design and Hierarchy using VHDL
Introduction to the FPGA and Labs
EET 1131 Unit 4 Programmable Logic Devices
CHAPTER 16 SEQUENTIAL CIRCUIT DESIGN
Digital Logic Circuits
EGR 2131 Unit 4 Combinational Circuits: Analysis & Design
Digital Fundamentals Floyd Chapter 3 Tenth Edition
LAB #6 Sequential Logic Design (Flip Flops, Shift Registers)
LAB #3 Design of Combinational Logic “The Trip Genie”
LAB #4 Xilinix ISE Foundation Tools VHDL Design Entry “A Tutorial”
Lab 2 : Overview Combinational System.
Lab02 :Logic Gate Fundamentals:
Basic Digital Logic.
ECE 4110–5110 Digital System Design
LAB #1 Introduction Combinational Logic Design
Digital Logic Circuits
Programmable Logic Devices: CPLDs and FPGAs with VHDL Design
Figure 5. 1 An example of AND-OR logic
ECE 448: Lab 6 Using PicoBlaze Fast Sorting Class Exercise 2.
ECE 3130 – Digital Electronics and Design
Digital Fundamentals Floyd Chapter 3 Tenth Edition
Digital Logic Circuits
LAB #2 Xilinix ISE Foundation Tools Schematic Capture “A Tutorial”
University of Maryland Baltimore County Department of Computer Science and Electrical Engineering   CMPE 212 Laboratory (Discussion 13) Hasib Hasan
Lab 0: Groups and Equipment
Presentation transcript:

ENG241/ Lab #41 ENG2410 Digital Design LAB #4 Design of Combinational Logic “The Trip Genie”

ENG241/ Lab #42 Lab Objectives  Understand the design flow of digital circuits.  Design a router for travelling salespeople.  Enter the design using both Schematic Capture and VHDL.  Implement the router using NEXYS 3 board.  Test and Debug your design and verify software simulation and hardware implementation.

ENG241/ Lab #43 The Trip Genie  A sales man travels between 4 cities.  6 highways connect the 4 cities.  Given two cities what is the shortest path for the sales man.

ENG241/ Lab #44 Implementation  Use the NEXYS 3 Switch for city selection.  Use the NEXYS 3 LEDs for highway indication.  The sales man should select two cities by flipping the corresponding switch.  The proposed path should be displayed on the LED.  Write the truth table of the trip genie.  Derive the combinational function for each highway.  Draw a schematic capture for each function.  Write VHDL code to describe each function.  Implement both in the NEXYS 3 board.

ENG241/ Lab #45 UCF File  You will use the following assignments: NET C1 LOC = T5; // left most slide switch on the NEXYS 3 board NET C2 LOC = V8; // Next slide switch on the board NET C2 LOC = U8; // third slide switch on the board NET C3 LOC = N8; // fourth slide switch on the board NET H1 LOC = T11; // left most LED on the NEXYS 3 board NET H2 LOC = R11; // Next LED on the board NET H3 LOC = N11; // third LED on the board NET H4 LOC = M11; // fourth LED on the board NET H5 LOC = V15; // fifth LED on the board NET H6 LOC = U15; // sixth LED on the board

Lab Report  Title Page – Group # and Names  Problem Statement  System Overview and Justification of Design  Circuit Diagram, Schematic  VHDL Code (Include COMMENTS)  Simulation Waveform  Problems Encountered and Recommendation ENG241/Lab #66

Academic Misconduct  Reports and demos are submitted as a group, but it is a SINGLE group effort  You may talk with other groups but sharing codes or reports is NOT ALLOWED  Copying reports from previous years is also NOT ALLOWED  If we find copying we are REQUIRED to report it