Possible Memory Redundancy Schemes (redundancy sub-team)

IO Redundancy Single IO to replace any Faulty IO in the memory –Based on shifted IO replacement –Very common –I covered that in my presentation Multiple IO to replace any Faulty IO in the memory –Each IO is mobile within the whole IO range –Difficult to implement in the memory –Should be independent of the memory Segmentation

Column Redundancy Single Column Redundancy that can replace any Column in memory –Implementation is not common C3 C0 C1 C2 RC r0 r4 r3 r2 r1 Q[7] Q[2] Q[1] Q[0] Q[6] C3 C0 C1 C2 C3 C0 C1 C2 C3 C0 C1 C2 C3 C0 C1 C2 ColMux Memory IO Columns Bit0 Bit6 Bit1 Bit2 Bit7

Column Redundancy Multiple Columns mobile across the whole memory array –Very rare to find in present SRAMs C3 C0 C1 C2 RC1 r0 r4 r3 r2 r1 Q[7] Q[2] Q[1] Q[0] Q[6] C3 C0 C1 C2 C3 C0 C1 C2 C3 C0 C1 C2 C3 C0 C1 C2 ColMux Memory IO Columns Bit0 Bit6 Bit1 Bit2 Bit7 RC2 Repair Mechanism

Column Redundancy Multiple Columns (Mostly 2 Columns) Restricted Mobility Within the IO –Replace only Consecutive Column with different Column Address bits C3 C0 C1 C2 RC r0 r4 r3 r2 r1 Q[7] Q[2] Q[1] Q[0] Q[6] C3 C0 C1 C2 C3 C0 C1 C2 C3 C0 C1 C2 C3 C0 C1 C2 ColMux Memory IO Columns Bit0 Bit6 Bit1 Bit2 Bit7 RC

Row Redundancy Single Row mobile across the Whole memory Array C3 C0 C1 C2 r0 r4 r3 r2 r1 Q[7] Q[2] Q[1] Q[0] Q[6] C3 C0 C1 C2 C3 C0 C1 C2 C3 C0 C1 C2 C3 C0 C1 C2 ColMux Memory IO Columns Bit0 Bit6 Bit1 Bit2 Bit7 RR Repair Mechanism

Row Repair Multiple Rows –Replace Specific Consecutive Number of Rows Starting at Even Row Address –Example: Two Rows Repair Unit

Row Repair Multiple Rows –Replace Specific Consecutive Number of Row starting at any Address –Example: Two Row Repair Unit C3 C0 C1 C2 r0 r4 r3 r2 r1 Q[7] Q[2] Q[1] Q[0] Q[6] C3 C0 C1 C2 C3 C0 C1 C2 C3 C0 C1 C2 C3 C0 C1 C2 ColMux Memory IO Columns Bit0 Bit6 Bit1 Bit2 Bit7 RR

Row and Column Most Common ones –Two Columns/IOs –Multiple Rows Row may or may not Span the whole Memory Column may or may not span the whole memory