Chuck Alpert Design Productivity Group Austin Research Laboratory Placement: Hot or Not Chuck Alpert Design Productivity Group Austin Research Laboratory

The State of Placement Placement is an old problem Rajeev: Today, the EDA academic community is not producing a lot of new ideas. Yes, at one time they did, but not today. “Lou Scheffer” : place-and-route is in reasonable shape

Placement Trends (my guess, not scientific) 2010 2012 Chip gate count: 21 M Largest Block: 1.5 M Chip gate count: 76 M Largest Block: 3.7 M

Placement is Hot Design sizes are exploding Designers are embracing automation like never before Secondary factors (power, area) become differentiating Wirelength is no longer primary Congestion Timing Power Clock-friendly

Generic Design Flow From Cadence

Vt Optimization? Swap to lower vt

Gate Sizing or Repowering b f e c a d a c e d b f

Buffering and Layer Assignment

Inverter Absorption / Decomposition f e c a d a e g f b

Composition / Decomposition w Out x w AOI nd2 B x Out nd2 A y nd2 C y nd2 C z z D D Courtesy: Louise Trevillian, founder of Logic Synthesis

Example Timing Closure “Optimization” Critical Path Optimization While 500 most critical nets still optimizable Gate sizing and vt Optimization Buffering on sub-tree Buffering on entire tree Congestion-aware layer assignment Suite of logic transforms Compression Optimization For remaining critical nets Gate sizing and vt Optimization Buffering, layer assignment on sub-tree

What Timing-Driven Placement Means Synthesis Traditional Placement Optimization Set Net Weights Timing-driven Placement Weight all nets? If not, what percent? What weight range? What netlist state for timing-driven placement?

Over Weight Can Destroy Congestion Initial After Timing-driven Placement Optimization Placement

Don’t Put Timing into Placement! Timing-driven Placement Flow Placement Timing Easy Constraints Placement Incremental Placement Constraint Generation Timing

Example Incremental Timing-Driven Placement Initial Final

Techniques Required for Timing-Driven Placement Identification of “easy” constraints Incremental Placement Shorten critical paths without hurting other paths Fast, incremental wirelength recovery Congestion-preserving detailed placement (don’t pack!) Getting pipeline latches right Meaningful timing model Interleave optimization (e.g., layer assignment)

Pipeline Latch Placement

Pipeline Latch Placement

Interference From Other Logic

Power-Aware Placement   #nets Switching Factor

Congestion Still Huge Problem Contests focus on congestion-driven placement Also need for incremental congestion repair Fast, accurate congestion modeling is key Placement A Placement B Router 1 Placement A Placement B Router 2

Placement Density Reasonable First Order

Local Congestion Effects (Pin Density) Before Spreading After Spreading Sc1 Plot with Stats

Handling Movebounds

Move Bound Challenges Don’t increase runtime High density / low density Inclusive or exclusive OverlappingSoft or absolute Different shapes Support high quantity

Datapath Placement Base Run Soft Alignment Forced Alignment net1 ( Fixed pins Datapath Placement LEGAL HPWL = 2385800 LEGAL HPWL = 2513500 LEGAL HPWL = 2461745 Base Run Soft Alignment Forced Alignment Courtesy: Sam Ward

Latch Huddling: Good For Clock Skew and Power July 26, 2012

Why Huddling is Good for Clocks More Clock Wire Less Clock Wire

All Object Movement (Before and After Huddling) (in tracks) 1-50 50-100 100-200 200-500 500+ Global Huddling Placement Incremental Huddling Placement

Global Clock Trees Challenge, can we separate three trees to prevent routing overlap?

Proposed Placement Framework Keep placement as a stand alone optimization Enrich it to handle constraints Add constraint generation step to guide placement Move bounds Power Switching factors Tightness of latch huddles Clock domain separation Use of hierarchical name space Alignment of datapath

Proposed Placement Flow Pre-Placement Constraints Placement (Global or Incremental) Clock Analysis Congestion Analysis Power Analysis Timing Analysis Constraint Generation

Do We Need to Write a Placer from Scratch? Clustering Clustered Global Flat Global Pin-Density Spreading Density Spreading Fast Congestion Analysis Congestion Mitigation Congestion-aware Detailed Placement Power Reduction

Chasing the Hot Topics Instead of trying to predict the next important problem Just ask (a designer)