COMPUTER ARCHITECTURE & OPERATIONS I Instructor: Hao Ji

Review Last Class Moore’s Law Classes of Computers Decimal, Binary, Octal, Hexadecimal Representations Program and Computer Compiler, Assembler, and Linker Components of a Computer Definition of Computer Performance Measure of Computer Performance

Review Moore’s Law The number of transistors that can be placed inexpensively on an integrated circuit doubles approximately every two years. Below Your Program Application software System software Two most important parts: Compiler and Operating System Hardware

Review Levels of Program Code High-level language Assembly language Machine language Function of Compiler Convert programs in high-level language to programs in assembly language Function of Assembler Translates assembly language into binary instructions

Review Components of a Computer Instruction Set Architecture (ISA) An abstract interface between the hardware and the lowest-level software. Specifies anything programmers need to know to make a binary machine language program work correctly, including instructions, I/0 devices, and so on.

Review Response time (AKA Execution Time) Total time required for a computer to complete a task Measured by time Throughput (AKA Bandwidth) Number of tasks done work done per unit time e.g., tasks/transactions/… per hour

Review Number Systems Decimal, Binary, Octal, and Hexadecimal Conversion Binary, Octal, and Hexadecimal to Decimal Decimal to Binary, Octal, and Hexadecimal

Review Order of magnitude billionthtrillionthpico-p 0.000,00 0,000, −12 −12 milliardthbillionthnano-n 0.000,00 0, −9 −9 millionth micro-µ 0.000, −6 −6 thousand th milli-m −3 −3 one ––

Review Order of magnitude billionthtrillionthpico-p 0.000,00 0,000, −12 −12 milliardthbillionthnano-n 0.000,00 0, −9 −9 millionth micro-µ 0.000, −6 −6 thousand th milli-m −3 −3 one ––

Performance Summary Computer Performance The BIG Picture The only complete and reliable measure of computer performance is time.

Performance Summary Performance of a program depends on Algorithm: affects IC, possibly CPI Programming language: affects IC, CPI Compiler: affects IC, CPI Instruction set architecture: affects IC, CPI, T c The BIG Picture

Today This Class Computer Performance Power Wall Assignment 1 Computer Logic Boolean Integrated Circuits, Decoder, Multiplexor, PLA, ROM, Bus

Power Trends §1.5 The Power Wall

Power Trends In CMOS technology §1.5 The Power Wall ×1000 ×30 5V → 1V

Reducing Power Suppose a new CPU has 85% of capacitive load of old CPU 15% voltage and 15% frequency reduction The power wall We can’t reduce voltage further We can’t remove more heat How else can we improve performance?

Uniprocessor Performance §1.6 The Sea Change: The Switch to Multiprocessors Constrained by power, instruction-level parallelism, memory latency

Uniprocessor Performance §1.6 The Sea Change: The Switch to Multiprocessors Constrained by power, instruction-level parallelism, memory latency

Multiprocessors Multicore microprocessors More than one processor per chip Requires explicitly parallel programming Compare with instruction level parallelism Hardware executes multiple instructions at once Hidden from the programmer Hard to do Programming for performance Load balancing Optimizing communication and synchronization

SPEC CPU Benchmark Programs used to measure performance Supposedly typical of actual workload System Performance Evaluation Corp (SPEC) Develops benchmarks for CPU, I/O, Web, … SPEC CPU2006 Elapsed time to execute a selection of programs Negligible I/O, so focuses on CPU performance Normalize relative to reference machine Summarize as geometric mean of performance ratios CINT2006 (integer) and CFP2006 (floating-point)

CINT2006 on Intel Core i7 920

SPEC Power Benchmark Power consumption of server at different workload levels Performance: ssj_ops/sec Power: Watts (Joules/sec)

SPECpower_ssj2008 on X5650

Fallacy: Low Power at Idle Look back at X5650 power benchmark At 100% load: 258W At 50% load: 170W (66%) At 10% load: 121W (47%) Google data center Mostly operates at 10% – 50% load At 100% load less than 1% of the time Consider designing processors to make power proportional to load

Amdahl’s Law Improving an aspect of a computer and expecting a proportional improvement in overall performance §1.8 Fallacies and Pitfalls Can’t be done! Example: multiply accounts for 80s/100s How much improvement in multiply performance to get 5× overall?

Pitfall: MIPS as a Performance Metric MIPS: Millions of Instructions Per Second Doesn’t account for Differences in ISAs between computers Differences in complexity between instructions CPI varies between programs on a given CPU

Concluding Remarks Cost/performance is improving Due to underlying technology development Hierarchical layers of abstraction In both hardware and software Instruction set architecture The hardware/software interface Execution time: the best performance measure Power is a limiting factor Use parallelism to improve performance §1.9 Concluding Remarks

Summary Performance Definition Power Trend Amdahl’s Law

Time for a Break (10 mins)

Review Last Session Power Wall IC manufacture Amdahl’s Law This Session Basic of Logic Design Next Session Combinational Logic

0s and 1s Modern Computers are Digital 1 Corresponding to a high voltage Signal Asserted Logical True 0 Corresponding to low voltage Signal Deasserted Logical False 0s and 1s are complementary 0’s inverse is 1 1’s inverse is 0

Units Bit 0 or 1 Byte (B) 8 bits ( ) Kilo (KB) 1024 bytes Mega (MB) 1,048,576 bytes Giga (GB) 1,073,741,824 bytes Tera (TB) 1,099,511,628,000 bytes

Combinational Logic and Sequential Logic Combinational Logic A logic system whose blocks do not contain memory and hence compute the same output given the same input Sequential Logic A group of logic elements that contain memory and hence whose value depends on the inputs as well as the current contents of the memory

Truth Table Example

Answer

Boolean Logic -- AND AND (Logical Product) Its output = 1, only if both inputs are 1 Truth table ABA·B

Boolean Logic -- OR OR (Logical Sum) Its output = 1 if either input = 1 Truth table ABA+B

Boolean Logic -- NOT NOT (Logical Inversion) or ~A The output is the opposite of the input Truth Table A~A

Order of Precedence Precedence Rule Parentheses (Highest) NOT AND OR Example

Boolean Logic Any Boolean Logic function can be implemented with only NOT, AND, OR functions NOT, AND, OR functions are the basic logic functions Others can be implemented by the basic logic functions NOT, AND, OR

Boolean Logic Laws Identity Law Zero and One Law Inverse Law Commutative Law

Boolean Logic Laws (cont.) Associative Laws Distributive Laws De Morgan’s Laws

How to prove a logical law? One approach: Truth table

How to prove a logical law? In Class Exercise: Truth table for de Morgan Laws

How to prove a logical law? In Class Exercise: Truth table for de Morgan Laws

Gates basic digital building blocks which correspond to and perform the basic logical functions AND OR NOT Complex digital functions that make up a computer are built from these basic digital building blocks

Simplification of NOT Gate

In Class Exercise Design a Combinational Logic to implement the following logical expression

NAND Its output = 1, only if both inputs are not 1 Boolean Expression: A B Truth Table The NAND functions has traditionally been the universal gate in digital circuits. It is simple to implement in hardware and can be used to construct the other gates. ABC

NOR Its output = 1, only if no inputs are not 1 Boolean Expression: A + B Truth Table ABC

XOR XOR is EXCLUSIVE-OR Its output = 1 if the inputs are different and equal 0 if all are the same. Boolean Expression: A  B Truth Table Equivalent to (AB) + (AB) = C A C B ABC

Summary 0s and 1s in Computer Boolean Logic NOT, AND, OR Boolean Logic Laws Truth Table Gates Basic Gates NOT, AND, OR Other Gates NAND, NOR, XOR

Time for a Break (10 mins)

Review Last Session Basic of Logic Design This Session Integrated Circuits Decoder Multiplexor PLA ROM Don’t Care Bus Next Class Design of ALU

Integrated Circuit Integrated Circuit (IC) A small electronic device made out of a semiconductor material Classifications SSI (small-scale integration) up to 100 electronic components per chip MSI (medium-scale integration) 100~3,000 electronic components per chip LSI (large-scale integration) 3,000~100,000 electronic components per chip VLSI (very large-scale integration) 100,0000 to 1,000,0000 electronic components per chip ULSI (ultra large-scale integration) More than 1 million electronic components per chip

Decoder A logic block that has n-bit input and 2 n outputs, where only one output is asserted for each input combination If the input is i (in binary), then output i is 1 others are 0

Decoder Example 3-8 Decoder

Multiplexor A selector The output is selected by an input control

Implementation of a Multiplexor

n-input Multiplexor A Multiplexor can have n-inputs Require selective inputs

n-input Multiplexor A Multiplexor can have n-inputs Require selective inputs Implementation of an n-input Multiplexor

Two-level Logic Try to Remember: Any Boolean Logic function can be implemented with only NOT, AND, OR functions We can also find that all logic functions can be written in a canonical form Sum of Product Logical Sum (OR) of terms joined by Product (AND) Product of Sum Logical Product (AND) of terms joined by Sum (OR)

Example Consider a logic function Equivalent to sum of products Equivalent to product of sums

In Class Exercise Considering the following truth table for D, write the function of D using sum of products

Answer Combinations that D is 1 Answer

Programmable Logic Array The sum of products representation corresponding to a common structured- logic implementation. Programmable Logic Array (PLA) Two stages of logic An array of AND gates (product terms) An array of OR gates

Programmable Logic Array Programmable Logic Array (PLA) Two stages of logic An array of AND gates (product terms) An array of OR gates

PLA Example Considering the following table, implement the PLA for D, E, F

Another PLA Representation Dot in the AND plane Input, or its inverse, occurs in the product term Dot in the OR plane Corresponding product term appears in the corresponding output

Read Only Memory Read Only Memory (ROM) Has a set of locations that can be read Contents of these locations are fixed Programmable ROM (PROM) Can be burnt using a device called a “ROM programmer” Erasable Programmable Read Only Memory (EPROM) Data in the ROM can be deleted under ultra-violet rays EEPROM (Electrically Erasable Read Only Memory) Data in the ROM can be erased by a simple electric current

ROM Height m inputs 2 m addressable entries (input lines) Width n outputs (functions) 2 n output bits mxn is the shape of the ROM

ROMs and PLAs PLA is partially decoded ROM is fully decoded Contains a full output word for every possible input combination Always contain more entries than PLA PLA (7 entries) ROM (8 entries – 1 unused)

Don’t Care We don’t care about the actual values Two types of Don’t Care Output Don’t Care We don’t care about the value of an output for some input combination Input Don’t Care An output only depends on some of the inputs Advantages of Don’t Care Easier to optimize the implementation of a logic function

Example of Don’t Cares Original Truth Table

Example of Don’t Cares Output Don’t Cares Input Don’t Cares

Array of Logic Elements Bus In logic design, a collection of data lines that is treated together as a single logical signal Shared collection of lines with multiple sources 32-bit wide 2-to-1 multiplexor

Summary Integrated Circuits Decoder Multiplexor PLA ROM Don’t Care Bus

What I want you to do Review Chapter 1 Review Appendix B (B1, B2, and B3) Work on your assignment 1