1 Random-Access Memory (RAM) Note: We’re skipping Sec 7.5 Today: First Hour: Static RAM –Section 7.6 of Katz’s Textbook –In-class Activity #1 Second Hour: Dynamic RAM Section 7.6 of Katz’s Textbook –In-class Activity #2

2 Recap 1.Edge-triggered Flip Flops 2.Sequential Modules Registers: esp. shift registers Counters: esp., Self-Starting Counters 3.Counter Design Procedure: 1.Draw a State Transition Diagram 2.Derive the State Transition Table 3.Choose a Flip-Flop 4.Derive the Flip-Flop Input Functions 5.Sketch the circuit 6.Add Refinements such as Power-up Reset

3 670 Q4 D1 D4 D3 D2 Q3 Q2 Q1 GW WA WB GR RA RB Recap: 4-by-4 Register File To write Register 1, set GW = 0 and (WB, WA) to (0,1) To read Register 2, set GR = 0 and (RB, RA) to (1,0) Can read and write simultaneously, No clock. Read or write when enables asserted. To write Register 1, set GW = 0 and (WB, WA) to (0,1) To read Register 2, set GR = 0 and (RB, RA) to (1,0) Can read and write simultaneously, No clock. Read or write when enables asserted. Read enable Data Out Read Select Data in Write enable Register 0 (4 bits) Register 1 (4 bits) Register 2 (4 bits) Register 3 (4 bits) Write Select

4 How it works Register 0 Register 1 Register 2 Register 3 MUX Read Select Data Out DMUX Read enable Write Select Data in Write enable

5 Random Access Memories (RAM) Same idea as a register file, but optimized for very many words. –Small RAM: bit words. –Larger RAM: 4 million 8-bit words. Some Changes: –No separate Read and Write Selects –Register select lines now called ADDRESS LINES –DATA IN and DATA OUT use shared wires –Designed such that multiple RAM chips can be connected together to build larger memory systems (e.g., 512 MB)

x 4-bit RAM Cell #0 Cell #1 Cell #2 Cell #1021 Cell #1022 Cell # = 2 10 cells  10 Address Bits 4 bits per cell  4 Data Bits

7 Typical RAM Chip To Read: To Write: To Read: To Write: Chip Select Write Enable 4 Bi-directional Data Lines (read & write) 10 Address Lines

8 Basic RAM Structure A0A0 A1A1 DMUX READ LINES SELECT LINES Memory Buffer Register IO 0 IO 1 IO 2 IO 3 WE WRITE LINES TRI-STATE LOGIC USED HERE

9 Practical RAM Designs 1024 x 4-bit RAM will have 1024 rows, and 4 columns –“Long, Thin Design” –Not very practical to fabricate –Long wires can make a chip run slowly Need to make the design more “square”.

10 A Squarer Design Address Buffers for Row Decoders A9 A8 A7 A6 A5 A4 Storage Matrix 64 x 16 Sense Amplifiers Address Buffers for Column Decoders A3 A2 A1 A0 Data Buffers CS WE I/O0I/O1I/O2I/O3 64 x 64 Square Array Amplifiers & Mux/Demux Some Addr bits select row Some Addr bits select within row Tri-State Data Out

11 Timing Diagrams We have 10 address bits, 4 data bits, and 2 control signals –A conventional timing diagram will be much too big! –Need some notation to represent groups of bits A 9 … A 0 Bits Can Change Here Bits Steady Here (May be 0 or 1)

12 Read Operation WE CS Address Data Out Valid Address Access Time The time it takes for new data to appear at the output Access Time The time it takes for new data to appear at the output New Notation! Center line means High-Z state (disconnected)

13 Other Timing Conventions Input SignalOutput Signal Must be steadyWill be steady high or low high or low High-to-lowWill be changing from changes permittedhigh-to-low during designated interval Low-to highWill be changing from changes permittedlow-to-high during designated interval Don't-CareState changing (Does not apply)Centerline represents high impedance (off) state

14 Write Timing Input Data Valid Address Data In Address WE CS Memory Cycle Time Data is sensed during this time

15 Do Activity #1 Now Explore the data sheet for a RAM chip, and answer a few questions The complete data sheets are on the course website (calendar tool, today’s date) For Qns 6 & 7, please stay consistent with the truth table on the third page of the data sheet. The circuit diagram on the first page may be a bit confusing.

16 Types of RAM 1.Static RAM (from first hour) Easy to understand/use: One D-type Flip Flop for each bit Fast Hard to scale up Occupies a lot of chip area Expensive Dynamic RAM Scalable: One tiny capacitor, and one transistor for each bit Slower than SRAM, but very cheap, and dense Hassles: Destructive readout Bit contents decay, so need to be refreshed periodically

17 SRAM Cell Data Word Enable i j Basic Idea: Try to minimize the complexity of each cell A fancy Master/Slave JK would be inappropriate here!

18 Dynamic RAMs (DRAMs) Word Line Bit Line Word LineBit Line To Read: assert Word Line, sense Bit Line Word LineBit Line To Write: assert Word Line, drive Bit Line Single Transistor Single Transistor (a switch), and a capacitor memory element Read-Out is Destructive! Read-Out is Destructive! Extra circuits needed to write back what was read Capacitor leaks, so ms Capacitor leaks, so Storage decays in ms Refresh Cycles Refresh Cycles needed

19 DRAM Refresh Refresh Frequency 4096 word RAM -- refresh each word once every 4 ms Assume 120 ns memory access cycle 1 in 8 DRAM accesses This is one refresh cycle every 976 ns (1 in 8 DRAM accesses)! But this RAM is really organized into 64 rows 1 in 500 DRAM accesses This is one refresh cycle every 62.5 µs (1 in 500 DRAM accesses) refresh once every 16 µs Large capacity DRAMs have 256 rows, refresh once every 16 µs

20 Do Activity #2 Now Due: End of Class Today. RETAIN THE LAST PAGE(S) (#3 onwards)!! For Next Class: Bring Randy Katz Textbook, & TTL Data Book Required Reading: – Sec 8.1, 8.2 of Katz This reading is necessary for getting points in the Studio Activity!