24 July 2002 Work In Progress – Not for Publication Modeling and Simulation ITWG Jürgen Lorenz - FhG-IISB ITWG/TWG Members H. Jaouen, STM * W. Molzer,

Slides:



Advertisements
Similar presentations
April 26-27, 2001 Ed Hall Work in Progress – Not for Publication Modeling and Simulation TWG Attendees Wim ShoenmakerEurope Gilles Le CarvalEurope Herve.
Advertisements

18 July 2001 Work In Progress – Not for Publication 2001 ITRS Test Chapter ITRS Test ITWG Mike Rodgers Don Edenfeld.
IRC Roll-Out/Plenary 4/4 Technology Node identified by xx90 –Minimum Half-Pitch of Metal 1 of either DRAM or Logic –Logic node presently being represented.
ITRS Winter Conference 2006 The Ambassador Hotel Hsin Chu Taiwan 1 ITRS IRC/ITWG Meetings HsinChu December 4, 2006 UPDATED Linda Wilson
DRAFT - NOT FOR PUBLICATION 16 July 2003 – ITRS Public Conference Lithography Update ITRS Meeting San Francisco, CA July
Modeling and Simulation TWG Hsinchu Dec. 6, Modeling and Simulation TWG Paco Leon, Intel International TWG Members: I. Bork, Infineon E. Hall, Motorola.
RF and AMS Technologies for Wireless Communications Working Group International Technology Roadmap for Semiconductors Radio Frequency and Analog/Mixed-Signal.
Litho ITRS Update Lithography iTWG July 2010.
ITRS Meeting. Stresa, Italy. April 19-20, G. Bomchil. ST Microelectronics 1 Integrated Project « CMOS backbone for 2010 e-Europe » NANOCMOS From.
Metrology Roadmap 2003 Update EuropeUlrich Mantz (Infineon) Mauro Vasconi (ST) JapanMasahiko Ikeno (Mitsubishi) Toshihiko Osada (Fujitsu) Akira Okamoto.
Work in Progress --- Not for Publication 6 December Interconnect Working Group ITRS 2000 Lakeshore Hotel, Hsinchu, Taiwan, R.O.C. 6 December 2000.
1 PIDS 7/1/01 18 July 2001 Work In Progress – Not for Publication P. Zeitzoff Contributors: J. Hutchby, P. Fang, G. Bourianoff, J. Chung, Y. Hokari, J.
Work in Progress --- Not for Publication 18 July 2001 Work In Progress – Not for Publication Interconnect Working Group 2001 Draft 18 July 2001 San Francisco.
4 December 2002, ITRS 2002 Update Conference Interconnect Working Group ITRS December 2002 Tokyo.
Metrology Roadmap 2000 Update EuropeAlec Reader (Philips) Wilfried Vandervorst (IMEC) Rudolf Laubmeier (Infineon) Rudolf Laubmeier (Infineon) JapanFumio.
DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference The 2004 ITRS Assembly and Packaging Roadmap Joe Adam TWG Co-Chair.
DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference PIDS Status and Key Issues: 2004 and 2005 ITRS Peter M. Zeitzoff for PIDS Technology.
Work in Progress --- Not for Publication DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference Interconnect Working Group ITRS 2004 Update.
DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference Modeling and Simulation ITWG Jürgen Lorenz - Fraunhofer-IISB ITWG/TWG Members H. Jaouen,
ITRS Summer Public Conference, July 15, San Francisco, CA, USA 1 Modeling and Simulation ITWG Jürgen Lorenz – Fraunhofer IISB – Chairperson M&S ITWG ITWG/TWG.
2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan Modeling and Simulation ITWG Jürgen Lorenz - Fraunhofer-IISB ITWG/TWG Members H. Jaouen, STM.
Modeling and Simulation ITWG San Francisco, July 24, July 2002 Work In Progress – Not for Publication Modeling and Simulation ITWG Jürgen Lorenz.
DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005 Modeling and Simulation ITWG Jürgen Lorenz – Fraunhofer IISB – chairperson M&S ITWG ITWG Members.
4 December 2002, ITRS 2002 Update Conference Modeling and Simulation ITWG Jürgen Lorenz - FhG-IISB ITWG/TWG Members H. Jaouen, STM * W. Molzer, Infineon.
ITRS Winter Public Conference, December3, Makuhari Messe, Japan 1 ITRS Summer Conference, July 12, 2012, San Francisco, CA, USA Modeling and Simulation.
Modeling and Simulation ITWG Tokyo, December 4, 2002 Modeling and Simulation ITWG Jürgen Lorenz - FhG-IISB ITWG/TWG Members H. Jaouen, STM * W. Molzer,
ITRS Summer Public Conference, July 14, 2010, San Francisco, CA, USA 1 Modeling and Simulation ITWG Bert Huizing – NXP – European M&S ITWG and IRC member.
ITRS Winter Conference 2006 The Ambassador Hotel Hsin Chu Taiwan 1 International Technology Roadmap for Semiconductors Assembly and Packaging 2006.
ITRS Winter Public Conference, December 9, Seoul, Korea 1 Modeling and Simulation ITWG Jürgen Lorenz – Fraunhofer IISB – Chairperson M&S ITWG ITWG/TWG.
ITRS Winter Conference 2006 The Ambassador Hotel Hsin Chu Taiwan 1 Modeling and Simulation ITWG Jürgen Lorenz – Fraunhofer IISB – chairperson M&S ITWG.
ITRS Summer Conference 2007 Moscone Center San Francisco, USA 1 DRAFT – Work In Progress - NOT FOR PUBLICATION Modeling and Simulation ITWG Jürgen Lorenz.
Packaging.
Aug 9-10, 2011 Nuclear Energy University Programs Materials: NEAMS Perspective James Peltz, Program Manager, NEAMS Crosscutting Methods and Tools.
ECE 6466 “IC Engineering” Dr. Wanda Wosik
Solar Cell Operation Key aim is to generate power by:
1 Lecture 5: IC Fabrication The Transistor Revolution First transistor Bell Labs, 1948 © Rabaey: Digital Integrated Circuits 2nd.
Optional Reading: Pierret 4; Hu 3
Advanced Computing and Information Systems laboratory Device Variability Impact on Logic Gate Failure Rates Erin Taylor and José Fortes Department of Electrical.
MASTER’S PROGRAM ELECTRICAL AND COMPUTER ENGINEERING Dr. Doug Lyon, and Dr. Jerry Sergent Program Co-Directors/ Chairs of CpE and EE Depts.
EZ-COURSEWARE State-of-the-Art Teaching Tools From AMS Teaching Tomorrow’s Technology Today.
Nano Technology for Microelectronics Packaging
OVERVIEW ON PROCESS & DEVICE SIMULATION
Silicon – On - Insulator (SOI). SOI is a very attractive technology for large volume integrated circuit production and is particularly good for low –
1 Chemical Engineering Tools for Semiconductor Fabrication David Cohen, PhD AIChE Norcal Symposium April 12, 2005.
Metallization: Contact to devices, interconnections between devices and to external Signal (V or I) intensity and speed (frequency response, delay)
Presented By : LAHSAINI Achraf & MAKARA Felipe.  Introduction  Difficult Challenges : > Difficult Challenges between 2013 – 2020 > Difficult Challenges.
RF Modeling of Sub-100 nm CMOS S.Yoshizaki 1, M.Nakagawa 1, W.Y.Chong 1, Y.Nara 2, M.Yasuhira 2*, F.Ohtsuka 2, T.Arikado 2**, K.Nakamura 2, K.Kakushima.
Text Book: Silicon VLSI Technology Fundamentals, Practice and Modeling Authors: J. D. Plummer, M. D. Deal, and P. B. Griffin Class: ECE 6466 “IC Engineering”
Numerical Boltzmann/Spherical Harmonic Device CAD Overview and Goals Overview: Further develop and apply the Numerical Boltzmann/Spherical Harmonic method.
Process Variation Mohammad Sharifkhani. Reading Textbook, Chapter 6 A paper in the reference.
1 Modeling and Simulation International Technology Roadmap for Semiconductors, 2004 Update Ashwini Ujjinamatada Course: CMPE 640 Date: December 05, 2005.
NUMERICAL TECHNOLOGIES, INC. Assessing Technology tradeoffs for 65nm logic circuits D Pramanik, M Cote, K Beaudette Numerical Technologies Inc Valery Axelrad.
IC Processing. Initial Steps: Forming an active region Si 3 N 4 is etched away using an F-plasma: Si3dN4 + 12F → 3SiF 4 + 2N 2 Or removed in hot.
AoE Project Nano-Process Modeling: Lithography modeling and device fabrication Philip Chan, Mansun Chan Department of ECE, HKUST Edmund Lam Department.
ADVANCED HIGH DENSITY INTERCONNECT MATERIALS AND TECHNIQUES DIVYA CHALLA.
EE141 © Digital Integrated Circuits 2nd Introduction 1 Principle of CMOS VLSI Design Introduction Adapted from Digital Integrated, Copyright 2003 Prentice.
Trends in IC technology and design J. Christiansen CERN - EP/MIC
Advanced Computing and Information Systems laboratory Nanocomputing technologies José A. B. Fortes Dpt. of Electrical and Computer Eng. and Dpt. of Computer.
Modelling and Simulation of Passive Optical Devices João Geraldo P. T. dos Reis and Henrique J. A. da Silva Introduction Integrated Optics is a field of.
Sandia NINE: Intel Expectations C. Michael Garner Technology Strategy.
UNCLASSIFIED Fundamental Aspects of Radiation Event Generation for Electronics and Engineering Research Robert A. Weller Institute for Space and Defense.
IH2655 Seminar January 26, 2016 Electrical Characterization,B. Gunnar Malm
ICT 25 Generic micro- and nano-electronic technologies Marc Boukerche DG CONNECT, A.4 Components.
Integrated Circuits.
Contact Resistance Modeling and Analysis of HEMT Devices S. H. Park, H
Contact Resistance Modeling in HEMT Devices
Atomistic simulations of contact physics Alejandro Strachan Materials Engineering PRISM, Fall 2007.
Atomistic materials simulations at The DoE NNSA/PSAAP PRISM Center
Optional Reading: Pierret 4; Hu 3
Presentation transcript:

24 July 2002 Work In Progress – Not for Publication Modeling and Simulation ITWG Jürgen Lorenz - FhG-IISB ITWG/TWG Members H. Jaouen, STM * W. Molzer, Infineon * R. Woltjer, Philips * G. Le Carval, LETI J. Lorenz, Fraunhofer IIS-B * W. Schoenmaker, IMEC * supported by EC User Group UPPER+ T. Wada, Toshiba K. Nishi, SELETE Japanese TWG 16 industrial members C. Riccobene, AMD L. Richardson, HP M. Giles, INTEL M. Orlowski, Motorola M. Meyyappan, NASA V. Bakshi, SEMATECH E. Hall, ex-chairperson/Motorola J.-H. Choi, Hynix K.H. Lee, Samsung S.-C. Wong, TSMC

24 July 2002 Work In Progress – Not for Publication Key Messages Update of key messages from 2001 ITRS: Technology modeling and simulation is one of a few enabling methodologies that can accelerate development times and reduce development costs: Assessment 25% in 2001, 35% in 2003, 40% in 2006 Strong cross-cut links to the other ITRS sections were established - major goal of ITWG activities to further extend these Accurate technology experimental characterization is essential. Modeling and simulation provides an embodiment of knowledge and understanding. It is a tool for technology/device optimization and also for training/education.

24 July 2002 Work In Progress – Not for Publication Equipment related Equipment/feature scale Lithography Feature scale Front End, Back End Device IC-scale Circuit elements Package modeling Interconnect performance modeling Materials Modeling Numerical Methods Technology Modeling SCOPE & SCALES (Chapter sub-sections in blue)

24 July 2002 Work In Progress – Not for Publication Trends / changes from 1999/2000 edition of ITRS Increased need for fundamental materials modeling and relating those results to electronic properties ( e.g. gate stack ) Need much better techniques / methodologies for exploring end of the roadmap issues. Stronger need for RF simulation methodologies. Need greater tie between models and chip design methodologies Need better analytical and characterization techniques to aid in the development of predictive models. Relevance of advanced numerical methods and algorithms increasing & more detailed in roadmap Key Messages ( cont)

24 July 2002 Work In Progress – Not for Publication Trends / changes from 2001 edition of ITRS New long-term challenge Compact modeling including statistics Adapt summary of issues in challenges list to current technical progress (e.g. skip 248 nm) Adapt details of near-term requirements to current technical progress: - esp. lithography status and roadmap - esp. multi-level hierarchical simulation ITWG actions in 2002 Update 2001 tables Further increase interactions with other ITWGs & impact of simulation Key Messages ( cont)

24 July 2002 Work In Progress – Not for Publication Difficult Challenges > 65 nm

24 July 2002 Work In Progress – Not for Publication Needs Efficient simulation of full-chip interconnect delay Accurate 3D interconnect model; inductance, transmission line models High-frequency circuit models that including –non-quasi-static effects –predictive noise behavior –coupling Predictive, scalable inductor model Reduction of high-frequency measurements needed for parameter extraction for active and passive devices Difficult Challenges High-Frequency Circuit Modeling (>5Ghz) (From Philips)

24 July 2002 Work In Progress – Not for Publication Difficult Challenges Modeling of Ultra Shallow Dopant Distributions (Junctions, Activation), and Silicidation Needs Dopant models & parameters (damage, high-concentration, activation, metastable effects, diffusion, interface and silicide effects) Characterization tools for ultra- shallow geometries and dopant levels Source: A. Claverie, CEMES/CNRS, Toulouse, France

24 July 2002 Work In Progress – Not for Publication Difficult Challenges Modeling of Deposition and Etch Variations, and Feature Variations Across a Wafer Needs Fundamental physical data ( e.g. rate constants, cross sections, surface chemistry). Reduced models for complex chemistries Linked equipment/feature scale models CMP (full wafer and chip level, pattern dependent effects) Next generation equipment /wafer models (e.g. 450 mm wafers ) Simulated across- wafer variation of feature profile for a sputter-deposited barrier.

24 July 2002 Work In Progress – Not for Publication Difficult Challenges Modeling of Lithography Technology Needs Predictive resist models (incl. mechanical stability) Resolution enhancement techniques; mask synthesis (OPC, PSM) 193 nm versus 157 nm evaluation and tradeoff methodologies. Next generation lithography system models: EUV, electron projection, maskless lithography Printing of defect on phase-shift mask: bump defect (top) vs. etch defect (lower)

24 July 2002 Work In Progress – Not for Publication Difficult Challenges Gate Stack Models for Ultra-thin Dielectrics Needs Electrical (breakdown, transport, reliability) & processing models for alternative gate materials and dielectrics Be able to model dielectric constant, surface states, defects, band gap,.... from process/material conditions. MSI - Band structure - Carrier effective mass... Direct Applications - Defect states - Leakage current - Impurity transport - Processing recommendations... Use atomistic models to predict physical and electronic properties of materials; eg, HfO 2. Potentials in a thin SiO 2 layer. 25 nm MIT MOSFET Density of States and IV Curve V DS =1.2V

24 July 2002 Work In Progress – Not for Publication Difficult Challenges < 65 nm

24 July 2002 Work In Progress – Not for Publication Needs Stress voiding Electromigration Piezoelectric effects Textures Fracture ( thin film and bulk) Adhesion Thermo-mechanical Stress in a 80x4 m 2 bamboo segment due to electromigration Difficult Challenges Thermo-Mechanical modeling (IMEC)

24 July 2002 Work In Progress – Not for Publication Other 2001 ITWG Recommendations General Support increased cross-discipline efforts that bring in experts from physics, chemistry, mathematics, and other fields to aid in solving these difficult challenges Need adequate research funds for universities and laboratories for directed long range research Explore ways of standardizing and / or opening up some of the universally used modeling and simulation modules so the focus is on value-add efforts Need improved methodologies for evaluating the impact of modeling and simulation Need a hierarchy of software tools - spread sheets to ab-initio

24 July 2002 Work In Progress – Not for Publication Other 2001 ITWG Recommendations Equipment Modeling Equipment suppliers should supply physical models and modeling information with equipment Process/Device Modeling Need continued modeling effort on improving process simulators Reliability models for circuit design and technology development

24 July 2002 Work In Progress – Not for Publication Other 2001 ITWG Recommendations Package Simulation Need co-design integration software tools - Thermal, mechanical, and electrical - Chip and package - RF capability Circuit Modeling Increased effort on industry standard circuit models Better methodologies for linking process and new device effects to designers I off /I on software tools - e.g leakage prediction

24 July 2002 Work In Progress – Not for Publication New 2002 ITWG Recommendations Tables modified in details New long-term challenge Compact Modeling Including Statistics Long-term requirement for emerging devices: Nanoscale simulation capability including accurate quantum models Long-term requirement for Package Modeling - electrical/optical models: Reliability prediction in coupled modeling

24 July 2002 Work In Progress – Not for Publication Thank You