DEPARTMENT OF COMPUTER SCIENCE & TECHNOLOGY FACULTY OF SCIENCE & TECHNOLOGY UNIVERSITY OF UWA WELLASSA 1 Microprocessor Architecture

2 Microprocessor is an integrated circuit that stores and manipulates information according to a set of instructions. In micro computers, one or more microprocessors serve as the CPU. The performance of microprocessors are expressed in terms of its, 1.Bandwidth-number of bits processed in a single instruction 2.Instruction set-set of instructions that can be executed 3.Clock Speed-number of executed instructions per second Introduction to Microprocessor 2

3 Externally the microprocessor connected to the system bus for transferring data and instructions to and from the components connected to it. External Architecture 3 Microprocessor Data Bus Address Bus Control Bus

4 The internal structure of a microprocessor consist of two components 1.Data path 2.Control unit Internal Architecture 4 Control unitData path Status signals Control signals Control outputs Data inputs Data outputs Control inputs

5 The data path contains circuits that only deal with data processing. E.g. Arithmetic circuits Multiplexers Decoders Registers …etc. The operations perform on data processing are called micro- operations. E.g. Arithmetic operations Logical operations Shifting operations Transferring operations Data path 5

6 Arithmetic operations R1R2+R3 This means add data stored in R2 and R3 registers and store the result in R1 register. To activate these micro operations some control signals are Needed. The combined values of all these control signals are known as a control word in a data path. control word is 16-bit binary value each bit indicate particular control signal Control Word R/W MDFS MBBAAADA

7 Control word for R1R2+R3 Control word required to execute this micro operation is Control Word… 7 FieldDAAABAMBFSMDR/W SymbolR1R2R3RegisterF=A+BFunctionWrite Control Word

8 Control unit determines; Sequence of micro operations in the data path. Type of control signals to activate micro operations. Control unit 8

9 History of Microprocessor Intel 4004(Intel’s 1 st microprocessor ) 1972-Intel 8008,Intel RCA MOTO 6800(Motorola) MOS 6502 (MOS Technologies) AMD 8080 (Advanced Micro Devices) Fairchild F8(Fair child) TITMS Ziglog z-80 Intel Intel 8086 Beginning of 80*86 Family

10 Intel 8086 processor Model 10 Execution Unit 16-bit Data bus 20-bit Address bus memory locations Speed-5Mhz/10MHz/15Mhz Register size-16bit Organized as two separate components 1.Bus Interface Unit(BIU) 2.Execution Unit(EU) Bus Interface Unit System Bus Instruction Pipeline Execution Unit

11 One of technique use in parallel processing. Same task cannot perform parallel but different tasks can perform parallel. E.g. Suppose a microprocessor perform following tasks (bus operations )on an instruction. Instruction Fetch=IF Instruction Decode=ID Instruction Execute=IE Memory Read=MR Memory Write=MW Pipelining 11

12 Pipelining… 12 InstructionsTime IFIDIEMRMW 2IFIDIEMRMW Different tasks can perform parallely.use 6 time units to perform 2 instructions. Non-pipelining Serial processing is used. For previous example needs 10 time units. Pipelining technique is more faster than non-pipelining technique.

13 Bus Interface Unit & Execution Unit 13 Bus Interface Unit(BIU) BIU is the 8086 interface to the outside-It is responsible for performing all external bus operations. BIU performs following bus operations 1.Instruction Fetching 2.Reading and writing of data into the memory and I/O device 3.Address generation 4.Instruction queuing Execution Unit(EU) The EU is responsible for decoding and executing instructions

14 Memory Organization microprocessor has 20 bit address bus. Therefore it contains 2 20 memory locations. If each memory location is 1 byte in size then 8086 microprocessor has memory space of 2 20 bytes=1MB Memory I organized as a linear byte array with consecutive address over the address range of FFFFFH-00000H 0 th byte ( ) th byte FFFFFH 00000H 00001H

15 Memory segmentation & Address generation 15 Physical address Memory Address Logical address Physical Address The actual address of the memory location Contain 20 bit address

16 Physical Address 16 Memory FFFF0H 003FFH 003FCH 00003H 00000H FFFFFH 1024 bytes 16 bytes Interrupt type 255 Interrupt type 0 Reserved for operations including a jump to the initial program and loading routine after a reset 8086 will always begin execution at location of FFFF0H Reserved for 256 possible interrupt type each type has it’s service routine pointed by a 4 byte pointer Interrupt Vector table 256 Int 256*4=1024bytes=1KB

17 Physical Address… 17 Registers in 8086 microprocessor can store only 16-bits. Therefore it is impossible to store 20-bit physical address in a register To overcome this problem 8086 microprocessor store the logical address of a memory location.

18 Logical Address 18 To develop the logical address we use memory segmentation. FFFFFH 00000H 64 KB In 8086 microprocessor the memory is partitions into several 64KB segments Each segment represent an independently addressable unit of memory consisting of 64KB consecutive storage locations. i.e consecutive bytes

19 These segments can be continuous,adjacent, disjoint or even overlapped Logical Address… 19 We can define any number of segments but only 4 segments can be active at a time. 1.Code segment –Store the program instruction code 2.Data segment –Store data for the program 3.Stack segment –Store interrupt and subroutine return address 4.Extra segment –Use as an extra data segment

20 Logical Address… 20 Each segment is assign a base address that identify it’s starting point. i.e. It's lowest address byte storage location This base address is need to store in the corresponding segment register in BIU. 64 KB Base Address

21 Logical Address… 21 Since registers can only store 16-bit address storing base address is a problem. To avoid this problem segments are partitioned in a such a way that it’s base address always contain zero for last 4 bits. e.g. 1FCA0,FFFC0….etc So the address is divisible by 16. Segments will only store base address without lower order hexa digit. e.g.1FCA01FCA(16-bit address)

22 Logical Address… 22 Offset The offset is the distance in bytes that the storage location of interest resizes from the base address of the corresponding segment. Therefore the lowest address byte in a segment has an offset of 0000H and highest has FFFFH. 64 KB Base Address Offset

23 Logical Address… 23 The logical address can be describe by a segment and the offset i.e. value of the segment register: value of the offset E.g. 1234:0011 values are representing using hexadecimal Even though the registers store the logical address of memory location the BIU use the physical address to access that memory location. So need to convert the logical address into the physical address of a particular memory location.

24 Converting logical address to physical 24 There are three steps in converting 1.Get the logical address segment register value: offset 2.Append a zero to the segment register value 3.Add the offset to the new segment register value Example: Generate the physical address for following logical address 1234H:0111H 0BA9:01CF

Register Set microprocessor contains 14,16-bit registers IP SP DX CX BX AX ES BP SI SS SR DI DS CS AHAL BHBL CHCL DHDL Instruction Pointer = Status Register(Flags) Segment registers Data registers Pointer registers Index registers General registers

26 Instruction Pointer 26 Instruction pointer store the offset of code segment. Instruction pointer always points to the location of the next instruction to be executed in the current code segment. Every time an instruction is fetched from the memory 8086 microprocessor updates the value in instruction pointer such that it points to the 1 st byte of the next instruction.

27 Segment Registers 27 There are four segment registers 1.SS-Stack segment registers 2.DS-Data segment registers 3.CS-Code segment registers 4.ES-Extra segment registers Four segment registers are use to store the base address of each segment These segment registers are user accessible which means that a programmer can change the values they store

28 Data Registers 28 There are four data registers 1.AX-Accumulator data register 2.BX-Base data register 3.CX- Counter data register 4.DX-Data data register Four data registers use for temporary storage of frequently use intermediate results. Advantage is the data can be accessed faster than they are in the memory Each of these registers can be access either as a whole 16-bit register for word data operations or as two 8-bit registers for byte data operations

29 Pointer Registers 29 There are two pointer registers 1.SP-Stack pointer register 2.BP-Base pointer register The content in SP and BP are use as offsets from the current value of the stack segment register SP-always represent the offset of the next stack location that can be access BP-always represent an offset relative to the stack segment. BP employed as the offset in an addressing called “Base addressing”

30 Index Registers 30 There are two index registers 1.SI -Source index registers 2.DI-Destination index registers Two index registers are use to hold offset addresses for instructions that access data stored in the data segment. Specially in “Indexed addressing mode” SI -Store an offset for source DI-Store an offset for the destination Index registers can also used as data registers in arithmetic and logical operations. These registers can only access as whole 16- bit registers but cannot access as two,8-bit registers.

31 Status Registers 31 ALU Status Registers Status register is connected to the ALU and it shows some of the outputs/results in ALU Status register is 16-bit register but only 9-bits use to show the results(only 9 bits are active)

32 Status Registers… 32 These 9 bits are divide into two types 1.Status flags 2.Control flags

33 Status Flags 33 1.Carry Flag: CF –CF is set to 1 if there is a carry out or a borrow in for the MSB e.g.- addition of 1101 and 1001 subtract 1101 from Parity Flag: PF –If number of 1’s in a binary code is even PF is set to 1. 3.Auxiliary Flag: AF –1 byte register can be divided into 2 parts as low nibble and high nibble,4-bits for each nibble.

34 Status Flags… 34 1 byte low nibble high nibble 4 bits AF is set to 1 if there is a carry out from the low nibble into high nibble or a borrow in from the high nibble into low nibble of the lower byte in a 16-bit word + _ Carry out Borrow in

35 Status Flags 35 4.Zero Flag: ZF –ZF is set to 1 if the result of an arithmetic or logical operation performed by the ALU is zero 5.Sign Flag: SF –SF is set to 1 if the result of an arithmetic or logical operation performed by the ALU is a negative number 6.Overflow Flag: OF –Sometimes the result of an arithmetic or logical operation cannot store in given register size. There can be overflow in the result.That is the result out of range. –OF is set to 1 if the result is out of range.

36 Control Flags 36 1.Trap Flag: TF –A microprocessor executes instructions in different modes. e.g. single step mode pipelined mode Single step mode Microprocessor execute one instruction at a time i.e. one instruction after another –TF is set to 1 if the 8086 microprocessor goes into single- step mode.

37 Control Flags 37 2.Interrupt Flag: IF –When an instruction executes there can be a break of the flow. –IF is set to 1 if there is an interrupt request 3.Direction Flag: DF Microprocessor can process strings. e.g. Consider a string “HELLO” stored in the memory H E L L O High address Low address

38 Control Flags 38 The processor can process this strings in 2 ways. 1.String data transfer from high address to low address HELLO 2.String data transfer from low address to high address OLLEH DF is set to 1 if the string instruction automatically decrements the address. –i.e. the string data transfers from high address to low address.