Digital Logic Design Lecture # 7 University of Tehran.

Slides:



Advertisements
Similar presentations
Chapter 3 Gate-Level Minimization
Advertisements

Minimization of Circuits
CS370 – Spring 2003 Hazards/Glitches. Time Response in Combinational Networks Gate Delays and Timing Waveforms Hazards/Glitches and How To Avoid Them.
ECE C03 Lecture 71 Lecture 7 Delays and Timing in Multilevel Logic Synthesis Hai Zhou ECE 303 Advanced Digital Design Spring 2002.
Glitches & Hazards.
Prof. Sin-Min Lee Department of Computer Science
RTL Design Introduction Decoder Encoder Multiplexer Tri-state Buffer
Figure 4.1. The function f (x1, x2, x3) =  m(0, 2, 4, 5, 6).
ECE 3110: Introduction to Digital Systems
Digital Logic Design Lecture # 17 University of Tehran.
K-Map Simplification COE 202 Digital Logic Design Dr. Aiman El-Maleh
Based on slides by: Charles Kime & Thomas Kaminski © 2004 Pearson Education, Inc. ECE/CS 352: Digital System Fundamentals Lecture 8 – Systematic Simplification.
1 Combinational Logic Network design Chapter 4 (continued ….)
KARNAUGH MAP Introduction Strategy for Minimization Minimization of Product-of-Sums Forms Minimization of More Complex Expressions Don't care Terms 1.
EECC341 - Shaaban #1 Lec # 8 Winter Combinational Logic Circuit Transient Vs. Steady-state Output Gate propagation delay: The time between.
Chapter 3 Simplification of Switching Functions
Give qualifications of instructors: DAP
ECE C03 Lecture 61 Lecture 6 Delays and Timing in Multilevel Logic Synthesis Prith Banerjee ECE C03 Advanced Digital Design Spring 1998.


Logic gate level Part 3: minimizing circuits. Improving circuit efficiency Efficiency of combinatorial circuit depends on number & arrangement of its.
EECC341 - Shaaban #1 Lec # 7 Winter Combinational Circuit Minimization Canonical sum and product logic expressions do not provide a circuit.
Lecture # 12 University of Tehran
Overview Part 2 – Circuit Optimization 2-4 Two-Level Optimization
Digital Logic Design Lecture # 8 University of Tehran.
Digital Logic Chapter 4 Presented by Prof Tim Johnson
B-1 Appendix B - Reduction of Digital Logic Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring Principles.
2-Level Minimization Classic Problem in Switching Theory
1 Chapter 5 Karnaugh Maps Mei Yang ECG Logic Design 1.
Chapter 3 Simplification of Switching Functions. Simplification Goals Goal -- minimize the cost of realizing a switching function Cost measures and other.
Department of Computer Engineering
Digital Logic Design Lecture # 3 University of Tehran.
The covering procedure. Remove rows with essential PI’s and any columns with x’s in those rows.
Optimization Algorithm
2-Level Minimization Classic Problem in Switching Theory Tabulation Method Transformed to “Set Covering Problem” “Set Covering Problem” is Intractable.
Chapter 3: Digital Logic Dr Mohamed Menacer Taibah University
UM EECS 270 Spring 2011 – Taken from Dr.Karem Sakallah Logic Synthesis: From Specs to Circuits Implementation Styles –Random –Regular Optimization Criteria.
Two Level Networks. Two-Level Networks Slide 2 SOPs A function has, in general many SOPs Functions can be simplified using Boolean algebra Compare the.
Circuit Minimization. It is often uneconomical to realize a logic directly from the first logic expression that pops into your head. Canonical sum and.
Computer Engineering (Logic Circuits) (Karnaugh Map)
Digital Logic Design Lecture # 19 University of Tehran.
Digital Logic Design Lecture # 14 University of Tehran.
ECE 3110: Introduction to Digital Systems Chapter #4 Review.
Prof. Hsien-Hsin Sean Lee
June 12, 2002© Howard Huang1 Karnaugh maps Last time we saw applications of Boolean logic to circuit design. – The basic Boolean operations are.
Digital Logic Design Lecture # 6 University of Tehran.
1 Gate Level Minimization EE 208 – Logic Design Chapter 3 Sohaib Majzoub.
Digital Logic (Karnaugh Map). Karnaugh Maps Karnaugh maps (K-maps) are graphical representations of boolean functions. One map cell corresponds to a row.
Lecture # 5 University of Tehran
CEC 220 Digital Circuit Design More Karnaugh Maps Monday, February 02 CEC 220 Digital Circuit Design Slide 1 of 11.
Chapter 3 Simplification of Switching Functions. Simplification Goals Goal -- minimize the cost of realizing a switching function Cost measures and other.
Lecture 3. Combinational Logic #2 Prof. Taeweon Suh Computer Science & Engineering Korea University COSE221, COMP211 Logic Design.
©2010 Cengage Learning SLIDES FOR CHAPTER 8 COMBINATIONAL CIRCUIT DESIGN AND SIMULATION USING GATES Click the mouse to move to the next page. Use the ESC.
Technical Seminar II Implementation of
©2010 Cengage Learning SLIDES FOR CHAPTER 8 COMBINATIONAL CIRCUIT DESIGN AND SIMULATION USING GATES Click the mouse to move to the next page. Use the ESC.
CHAPTER 3 Simplification of Boolean Functions
CSC205 Jeffrey N. Denenberg Lecture #5
ECE 2110: Introduction to Digital Systems
Lecture #6 EGR 277 – Digital Logic
ECE 3110: Introduction to Digital Systems
COMP211 Computer Logic Design Lecture 3. Combinational Logic 2
Hazard.
Overview Last Lecture Conversion of two-level logic to NAND or NOR forms Multilevel logic AOI and OAI gates Today Timing and hazards Multiplexers and demultiplexers.
CSE 370 – Winter 2002 – Logic minimization - 1
Optimization Algorithm
Introduction to Digital Systems
Chapter 10.3 and 10.4: Combinatorial Circuits
Overview Part 2 – Circuit Optimization
ECE 352 Digital System Fundamentals
Karnaugh maps Last time we saw applications of Boolean logic to circuit design. The basic Boolean operations are AND, OR and NOT. These operations can.
Presentation transcript:

Digital Logic Design Lecture # 7 University of Tehran

Outline Verilog More on Minimization by KM Don’t Care Terms Hazard Quine-McCluskey Method for Minimization

Verilog Continuing our discussion on Verilog, consider for instance a situation where we want to simulate a circuit such as the below shown. The code for this circuit would look like this: module function(a, b, c, d, w); input a, b, c, d; output f; wire w, y; and #(, ) u1(w, a, b); nand #(, ) u2(y, c, d); nor #(, ) u3(f, y, w); endmodule

Verilog (continued…) As you can see we can also include timing conditions for the gates as we did for transistors. The only difference is that we have at most 2 values showing the transition to 1 and transition to 0 delay times. There is no third value included because at gate level, transition to Z doesn’t have any meaning.

More on Minimization by KM We saw before how switching functions of up to 5 variables could be minimized using karnaugh maps. We will now show a 6 variables karnaugh map which is practically the largest karnaugh map we will ever use.

More on Minimization by KM (continued…) Adjacency rules are maintained as they were before. We can consider these four 4 variables maps stacked onto each other to help us visualize the adjacency rules between them. For instance, the term representing the four shown minterms would be This will be the largest karnaugh map we will ever use. Using karnaugh maps for switching functions of a larger number of variables would be impractical.

Don’t Care Terms In some functions, not all combinations of the used number of variables can occur. For instance when the input of a circuit is in BCD form, we will only be receiving inputs of the binary numbers 0000 through 1001, in other words we don’t care what the outputs to these particular conditions are, because they will not be occurring in our problem. When using a karnaugh map for minimization, these terms need not be covered necessarily and are only considered to be 1 if they help us in covering a larger arena with certain maps.

Don’t Care Terms (continued…) Note: Don’t care terms can not be used to distinguish between implicants and prime implicants. Note: Don’t care terms are not specified to be 0 or 1 until after a mapping has been done. It is also not necessary to consider the same don’t cares of a function that we have mapped as 1s in a SOP form, as 1s when mapping for a POS form. Consider for instance a case where we want to map the following karnaugh map for both SOP and POS form.

Don’t Care Terms (continued…)

Hazard Consider the following gate structure and its timing diagram (numbers on the gates show their delays):

Hazard (continued…) As we can see after a period of time and after changes have occurred, ‘y’ finally becomes 1. But for a small period of time, both of the gates have 0 on their outputs and thus cause ‘y’ to become 0 for 5 ns.

Hazard (continued…) Let’s look at what has happened more carefully: When the input of the circuit changes from 111 to 101, there shouldn’t actually be any change in the circuit’s output theoretically but because the delay of one of the two paths which ‘b’ is passing through to reach the output is more than the other, an unwanted pulse known as a glitch (or a 1-hazard in this case) is occurring where the output drops to 0 for 5 ns.

Hazard (continued…) We would have never observed such problems by only taking the switching algebra to mind, because this is a problem caused by the physics of our realization. What we want to know is how to identify and solve such problems before they occur, that is while they are still potential hazards. Consider for instance the karnaugh map of the last example that we have:

Hazard (continued…) To identify where potential hazards may occur from a KM, we must realize the fact that there can only be a hazard where an input is passed through to the output by more than one path. That is, on the KM, potential hazards only occur when we move from one 1 to another when they are not covered in one map. Whether or not this potential hazards turn into reality depends on the actual gate timings. To eliminate such potential hazards we must map those particular 1s thus using redundant map.

Hazard (continued…) Example: Potential hazards: 0101   0011 In these cases, we can’t be sure that hazards occur, but because of the disjoint mapping, it is possible. To eliminate this chance, we can add the map and write

Hazard (continued…) Quote: 0-hazards can occur in the same shape as 1- hazards but in POS representation of the circuit. Another type of hazard, which occurs less often than the hazards mentioned so far (static hazards) is called a dynamic hazard. There are two kinds of dynamic hazards with two different waveforms which are :

Hazard (continued…) It can be proven that dynamic hazards are results of static hazards. For instance it is quite obvious that the second waveform can occur as a result of two static hazards that occur after each other. The reason dynamic hazards occur less often is that they often involve a change in 2 variables of the switching function in a very short period or at one instance.

Quine-McCluskey Method for Minimization Up until now, all methods of minimization we have used were practical for a small number of variables. For example, the KM was practical for at most 6 variable functions. For functions of a larger number of variables, we need method that can be applied to computer based minimization. One method that we can use for this means is the Quine-McCluskey method that uses the following steps. For example:

Quine-McCluskey Method for Minimization (continued…) It is obvious that only minterms that differ in one variable’s value can be combined. Thus we list our minterms so that they are in groups with each group having the same number of 1s. So the first step is ordering the minterms according to their number of 1s (0-cube list) as shown below for this example (In such groups, only minterms residing in adjacent groups have the chance to be combined.):

Quine-McCluskey Method for Minimization (continued…) Compare minterms of a group with those of an adjacent one to form 1-cube list. When doing the combining, we put checkmark alongside the minterms in the 0-cube list that have been combined.

Quine-McCluskey Method for Minimization (continued…) We do the same combination procedure of comparing adjacent group minterms to form 2-cubes, 3-cubes and so on. While doing so, it can be seen that only minterms of adjacent groups have the chance of being combined which have an X in the same position.

Quine-McCluskey Method for Minimization (continued…) PIs are those terms left without checkmarks. After identifying our PIs, we list them against the minterms needed to be covered in the following manner :

Quine-McCluskey Method for Minimization (continued…) To find a minimal cover, we first need to find essential PIs. To do this we need to find columns that only have one checkmark in them, the according row will thus show the essential PI. After identifying essential PIs, that are necessarily part of the cover, we cover any remaining minterms using a minimal set of PIs. In this example: