Recent RD50 studies have shown that silicon irradiated at these levels still delivers a signal of ~ 8ke - / MIP LHCb upgrade rationale. After collecting 10 fb -1 (~2015?) at the standard luminosity of 2*10 32 /cm 2 /s, the time-to- double-statistics will be 3 years. LHCb wants to increase the b-event yield by a factor >10 to efficiently address remaining open physics questions and aims to collect 100 fb -1 in 5 years. Increasing the luminosity x 10 is rather ‘easy’ for LHCb (enhanced beam focusing can be introduced at ‘any’ time and does not require an LHC- upgrade). But : many b-event yields do not increase with luminosity, rather saturate...! LHCb has a (single !) hardware trigger level (L0), necessary to reduce the event-rate to 1 MHz, which is a built-in limitation of the front-end electronics readout. To handle an increased collision rate, but constant output rate, the L0-rejection must be increased by raising the thresholds, leading to less signal efficiency (especially calorimeter triggers). Electronics for the LHCb VELO upgrade. Presented at: Topical workshop on electronics for particle physics (TWEPP09) VELO upgrade environment: VELOPIX asic Testbeam results. Presented by: Jan Buytaert (CERN) on behalf of the LHCb VELO collaboration September 2009 STRIP : the current r-phi strip layout is a viable solution, since even at 2*10 33 /cm 2 /s luminosity, the expected average strip occupancy is not exceeding 2% and after 100 fb -1 the expected S/N ~ 8 (8ke - /1ke -) is still sufficient for tracking and triggering. The readout asic (‘Beetle’) must be replaced by a new asic with: -integrated 6-bit ADC per strip, -correlated noise correction algorithm (digital). -cluster extraction (digital) Initial studies have been done and it is considered a safe ‘fall- back’option, in case the pixel solution is unworkable, or introduces too much material into the acceptance Pixel or Strip sensor Readout challenge. Note: the mean number of interactions per 'non-empty' event only increase from 1.2 to 4 for a factor 10 increase in luminosity. Detector granularities are largely sufficient and the upgrade focus is mainly on the FE electronics and DAQ. Solution: Only a more sophisticated trigger can maintain good efficiencies. Decided not to rebuild new & more complex L0-trigger electronics, but execute the trigger algorithms on all data in software. A new DAQ system must transfer all, zero-suppressed front-end data straight into a large computer farm, through a huge optical network & router. All front-end electronics must be adapted or rebuilt to digitize, zero- suppress and transmit event data at 40MHz. Since the FE-electronics of the trackers (IT,OT,TT and VELO) and of the RICH is integrated on detectors, this requires new, possibly enhanced detectors. Calorimeters and muon detectors can be retro-fitted with new FE electronics. Particle occupancies will vary as r At r = 1 cm and L=2*10 33 /cm 2 /s the highest simulated occupancy is 4.8 particles/cm 2 /event Fit to Ar -1.9 for different luminosities radius (cm) JC Wang Particle Hits / Event / cm 2 Severe irradiation damage: At 7 mm from beam the TID will be 370 MRad or 8 x n eq /cm Radius (cm) Dose after 100 fb -1 n eq cm -2 x TID (MRad) 7 mm DUT position and angle controlled remotely by stepper motors 6 plane Timepix Telescope + DUT Timepix was used in a 120 GeV pion beam, with the aim of : 1. characterizing the pixel digitization of charge-to-TOT (time- over threshold) for high momentum particle tracking; 2. measuring cluster sizes and track resolution at different track incidence angles; 3. measure time-walk effects. These data will serve as input specifications to the Velopix design. Fraction of cluster with sizes N versus track angle N=1 N=2 N=3 N=4 track angle (degrees) occurrence Pixel and Cluster Charge spectra. time-over-threshold ( 25 ns units) Front-end router CPU-farm 40 MHz upgrade DAQ L0-trigger L0-buffer 1MHz current DAQ Front-end router CPU-farm Tell40Tell1 PIXELS : the TIMEPIX concept of pixels is an attractive solution for the VELO upgrade, because: the extremely low occupancy (< 2 ppm) environment is ideally suited to the time-over-threshold conversion, as the efficiency will not suffer from the relatively large (1us) dead time. the square pixel (55um x 55um) results in equal spatial precision in both directions, removing the need for a double sided modules and saving a factor 2 in material. it is a very ‘economic’ way (power & space) to obtain >6 bit digitization. Through-silicon-via technology allows a novel module assembly. But important issues must be solved: the pixel chip heat dissipation aggravates the thermal run- away risk of the irradiated sensor. the internal readout from the 256x256 pixel array at 40MHz is very challenging ! 150  m ASIC 50  m Al ground plane power tape 200  m diamond window in diamond 55x55  m pixels (150  m SI) 800x55  m pixels under inactive part of chip wire bonds TSVs Prototype Velopix module. 2.5  m Estimated track contribution to residual Unbiased track residuals Angle (degrees) Residual (micron) Timepix: 55  m pitch Luminosity (cm -2 s -1 ) L = Current VELO L = L = L = Upgraded VELO A  Tell40 : regroups clusters from same beam crossing adds network layer possibly rejects events (‘throttle’) Distribution of time-differences between pixels of same cluster (25 ns units) time difference (25 ns units) occurrence A VELO pixel readout chip will be derived from the TIMEPIX asic. The main modifications are: 1.replace ‘shutter’ based acquisition/readout scheme by continuous, dead-timeless operation. 2.sustained readout of pixels with maximal average particle flux = 5 particles/cm 2 /25ns 3.power consumption must stay within1-2 W 4.pixel functionality: reduce TOT count range and resolution : 4 to 6 bit scheme is sufficient. reduce rise time to reduce time-walk effects. add bunch identification to hit. Design and simulation of a fast column readout has started. The 256x256 array is partitioned in 32 “EOC block”, each consisting of 8 columns : HeaderEOC block idcolumn hit patternn x pixel data 4 bit5 bit8 bitn x 22bit (n=1...8) data packets: row addressTOT datatimestamp 8 bit4 bit10bit pixel data :No packet is transmitted if n=0, else data size = (17 + n*22) bit. 8 colums (256 pixels) EOC logic EOC block controller Output logic EOC block Comparator output Comparator threshold LE TE ToT = TE - LE Q ToT = f(Q) Conversion by time-over-thresholdImprovements are under study: - a ‘Tetris-style’ readout would be better suited to the non-uniform pixel occupancy. - to cluster pixel data inside the pixel array before readout would reduce the data size, since bunch-id and pixel address are not repeated. - to cluster hits in time, for on-chip time-walk correction. Efficient heat removal will be required to avoid thermal runaway. A diamond cooling substrate is a candidate solution. The electronics must be of sufficiently low noise to cope with the reduced signal. Vacuum tank 20 x Differential copper links ~ 2m vacuum feed-throughs Electro-optical 20 x optical links ~60m Tell 40 Network interface 1 module readout slice 320 Mbit/s For a full module : total data rate = 63.4 Gbit/s or 20 data 3.2 Gbit/s. For the full VELO system (42 modules) : total data rate = 2700 Gbit/s 840 data 3.2 Gbit/s. For 1 Velopix asic : maximum data rate = 10.9 Gbit/s or 4 data 3.2 Gbit/s. average particle rate per bx and average data rates (Gbit/s) for the Velopix asics, at the highest luminosity (L=20*10 32 /cm 2 /s) and with an average cluster size= mm LHC beam 200  m Diamond substrate Cooling channel Prototype strip module. muon channels hadronic channels G. Casse et al.