Two’s Complement Number wheel for 4 bit numbers

Addition

Subtraction

Booth’s Theory 00111110 25+24+23+22+21  26-21 Looks for transitions from 0-1 (add) and 1-0 (minus) Uses a “phoney” bit -1 (i.e. to the right of bit 0) Assumes two’s complement signed numbers extend bit width of unsigned numbers if necessary.

Booths Algorithm

Two’s complement multiplication examples

Division

CCS compiler w/ 2’s complement #device PIC16F877 *=8 ADC=8 void main() { signed int c; c=-4; } 0000 3000 movlw 0x0 0001 008A movwf 0xA 0002 2804 goto MAIN 0003 0000 nop 0004 0184 MAIN clrf 0x4 0005 301F movlw 0x1F 0006 0583 andwf 0x3 0007 30FC movlw 0xFC 0008 00A1 movwf 0x21 0009 0063 sleep

Addition/Subtraction #device PIC16F877 *=8 ADC=8 void main() { signed int c; signed int b; c=-4; b=c+2; } 0000 3000 movlw 0x0 0001 008A movwf 0xA 0002 2804 goto MAIN 0003 0000 nop 0004 0184 MAIN clrf 0x4 0005 301F movlw 0x1F 0006 0583 andwf 0x3 0007 30FC movlw 0xFC 0008 00A1 movwf 0x21 0009 3002 movlw 0x2 000A 0721 addwf 0x21,W 000B 00A2 movwf 0x22

incfsz resulthi,F ; if resulthi is 0 after the increment ; ... don't do the addition addwf resultlo,F ; resultlo = resultlo + W movwf resulthi ; resulthi = resulthi + W decf R_hi,F ; do the decrement after btfsc STATUS,C ; If no carry ... subwf Q1_lo,W ; W = Q1_lo - Q2_lo subwf Q1_hi,W ; W = Q1_hi - Q2_hi Borrow subwf Q1_hi,W ; W = Q1_hi - Q2_hi btfss STATUS,C ; need to borrow? Addgood movf datalo,W ; W = datalo movf datahi,W ; W = datahi addwf resulthi,W Subrgd movf Q2_lo,W movf Q2_hi,W goto Borrow movwf R_lo movwf R_hi goto Done Done return

Multiplication & Division #device PIC16F877 *=8 ADC=8 void main() { signed int c; signed int b; c=-6; b=c*5; b=c/3; } goto vs. call? 0063 0184 MAIN clrf 0x4 0064 301F movlw 0x1F 0065 0583 andwf 0x3 0066 30FA movlw 0xFA 0067 00A1 movwf 0x21 0068 0821 movf 0x21,W 0069 00A3 movwf 0x23 006A 3005 movlw 0x5 006B 00A4 movwf 0x24 006C 2804 goto 0x4 006D 0878 movf 0x78,W 006E 00A2 movwf 0x22 006F 0821 movf 0x21,W 0070 00A3 movwf 0x23 0071 3003 movlw 0x3 0072 00A4 movwf 0x24 0073 283B goto 0x3B 0074 0878 movf 0x78,W 0075 00A2 movwf 0x22 0076 0063 sleep

rrf R_hi,F ; shift over for the next addition Umul rrf M2,F ; rotate into carry to check bits btfsc STATUS,C ; if carry set i.e. bit was 1 clrf R_hi ; Clear result location movf M1,W ; initialize W with M1 decf cntr,F ; check the loop count ; No checks made for M1 or M2 equal to zero movlw 0x08 ; setup loop count addwf R_hi,F ; ... we add ; 8x8 unsigned multiply routine. btfss STATUS,Z rrf R_lo,F clrf R_lo movwf cntr goto Umul return

CCS Compiler Integer multiplication Repeated addition store result sign convert both integers to unsigned store one integer in W For each bit in integer; if set add W to the result rotate result if result sign is negative, convert the result

BCD Decimal: Facilitates easy conversion to/from human input BCD: Each digit represented by an n-bit binary number Packed BCD: 2 digits represented in a single byte 5 9 0 1 0 1 1 0 0 1

ASCII Visible Character Codes Control Codes From: http://www.mindspring.com/~jc1/serial/Resources/ASCII.html ASCII Visible Character Codes Control Codes Physical Communication Control Logical Communication Control Physical Device Control Physical Device Format Effects Code Extenders Information Separators

Floating point arithmetic SBE ; B is known

CCS compiler floating point numbers

CCS floating point example #device PIC16F877 *=8 ADC=8 void main() { float c; c=1.25; } 0000 3000 movlw 0x0 0001 008A movwf 0xA 0002 2804 goto MAIN 0003 0000 nop 0004 0184 MAIN clrf 0x4 0005 301F movlw 0x1F 0006 0583 andwf 0x3 0007 307F movlw 0x7F 0008 00A1 movwf 0x21 0009 3020 movlw 0x20 000A 00A2 movwf 0x22 000B 3000 movlw 0x0 000C 00A3 movwf 0x23 000D 00A4 movwf 0x24 000E 0063 sleep

Should we use floating point with the PIC? VERY LONG programs, which are processor intensive try CCS assembler float c=2.3; c=2.3; c=2.3*1.25; Possible Alternatives lookup tables fixed point representation (factored arithmetic) See: http://www.phanderson.com/PIC/16C84/calc_disc_1.html

Memory Wars Bit Numbering Bit Ordering Data Alignment End-ian-ness

Changing bit-widths 2’s complement BCD ASCII Floating point extend/reduce the sign bit BCD fill with 0’s at front ASCII defined as 7-bit Floating point fill significand (mantissa) at end add the change in offset to exponent

Assembler Programming Directives, Good Practice LIST p=<target microcontroller> #include <file> predefined constants for target microcontroller <const> EQU <value> define own constants (can be used for the addresses of variables) Labels in the first column nop at address 0x00 (ICD) goto at address 0x01 (Interrupts) ORG <addr> next code line appears at this address BANKSEL <addr> switch banks to that for the specified address sleep at the end of the main routine Be careful that main code does not “accidentally” run into subroutine code and vice versa END -- end of the code

Table Creation/Lookup table addwf PCL, F ; add W and store in PCL retlw B'00000001' ; return 1 in W if W = 1 retlw B'00000011' ; return 3 in W if W = 2 retlw B'00000110' ; return 6 in W if W = 3 retlw B'00000010' ; return 2 in W if W = 4 end DT “Bat”,0 retlw A’B’ retlw A’a’ retlw A’t’ retlw 0

Table Creation/Lookup BSF STATUS, RP1 ; BCF STATUS, RP0 ;Bank 2 MOVF ADDR, W ;Write address MOVWF EEADR ;to read from BSF STATUS, RP0 ;Bank 3 BCF EECON1, EEPGD ;Point to Data memory BSF EECON1, RD ;Start read operation MOVF EEDATA, W ;W = EEDATA DE (8-bit data in the EEPROM memory) ORG 0x02100 DE “Bat”,0

Table Creation/Lookup BSF STATUS, RP1 ; BCF STATUS, RP0 ;Bank 2 MOVF ADDRL, W ;Write the MOVWF EEADR ;address bytes MOVF ADDRH,W ;for the desired MOVWF EEADRH ;address to read BSF STATUS, RP0 ;Bank 3 BSF EECON1, EEPGD ;Point to Program memory BSF EECON1, RD ;Start read operation NOP ;Required two NOPs NOP ; MOVF EEDATA, W ;DATAL = EEDATA MOVWF DATAL ; MOVF EEDATH,W ;DATAH = EEDATH MOVWF DATAH ; DA (14-bit data in the program memory) ASCII strings packed two chars to a word DA "abcdef" will put 30E2 31E4 32E6 3380 into program memory DA 0xFFFF will put 0x3FFF into program memory

Page IV-6, Q.1 Original Code: 1 case: 2+8+2 216-1 cases: 2+9+2 Avg. Cycles: 9 Max. Cycles: 9 Modified Code: Remove 1 line Swap 2 lines 216-1 cases: 2+7+2 Avg. Cycles: 7 Max. Cycles: 8 movf countl,F btfsc STATUS,Z decf counth,F decf countl,F movf countl,F movf count,F goto Bz goto Nbz Redundant s

Page IV-6, Q.1 Tutorial Group Solution Subtraction of 1 can never result in both a borrow and a zero result i.e. if the carry flag is clear, the zero flag is never set. Early Exit C, Z 256 cases: 2+5+2 C, Z 256*254 cases: 2+5+2 Remaining C, Z 255 cases 2+8+2 1 case: 2+9+2 Avg. Cycles: 5 Max. Cycles: 9 movlw 1 subwf countl,F btfss STATUS,C decfsz counth,F btfss STATUS,Z goto Nbz movf counth,W btfss STATUS,Z goto Bz

Tutorial Group page IV-6 Q. 6 To divide an x-bit dividend by a q-bit divisor using Booth’s like division make an (q+x) bit number for the q-bit remainder and x-bit quotient initialise the uppermost q-bits with the sign bit of the dividend, and the lower x-bits with the dividend Loop for x times: arithmetic left shift the (q+x) bit number if the sign is the same as(different from) the divisor subtract(add) the divisor from(to) the uppermost q bits if the result sign is different from the original sign; undo if the result sign is the same as the original sign OR the whole (q+x) number is 0; set the LSB of the (q+x) bit number to 1 Remainder is top q-bits. If the divisor and dividend signs are same (different), the answer is the (complement of ) bottom x-bits