A Requirements-Driven PLD Design Flow MAPLD 2009 Dominic Lucido Sr. Applications Engr

Nucleus Secure KernelNucleus Secure KernelFireControl Mentor Offers Complete Electrical Systems Design Automation Boardstation Expedition Data Management Capital Harness System HDL Designer Precision synthesis ModelSim simulator FormalPro Questa adv verification TestKompress DFT Calibre phys verification SystemVision PCB Design FPGA/ASIC Design EWIS Design Electro-Mechanical System Simulation Embedded SW

n... is needed by many Safety Critical & Mission Critical Industries: — Commercial Aviation — Military — Space — Medical Electronics — Automotive — Railway — Robotics — Industrial Controls — Banking Systems — Cruise Ships — Shipping Requirements Driven Development Process

DO-254 in the Aircraft Certification Process Timeline ~2 years Type Certificate(ATC/TC/STC) The FPGA/ASIC is approved only as part of an FAA approved equipment installation TC form describes every item on aircraft Components now “DO-254 certified” DO-254 Compliance DER form submitted to FAA recommending approval of the ASIC/FPGA System Safety Assessment Criticality of systems determined Design assurance level (DAL) A-E assigned DAL of Component DAL handed down to component Determines DO-254 requirements FPGA/ASIC Built to DO-254 standards as reviewed by DER

Review: Principles of DO-254 n DO-254 Lifecycle n DO-254 Key Concepts — Detailed planning captured in PHAC — Requirements driven flow n Requirements tracing — Thorough verification — Flow under strict CM — Audits against PHAC n Internal QA reviews n External SOI audits — Proof of compliance shown through artifacts 5 Requirements Capture Requirements Capture Conceptual Design Conceptual Design Detailed Design Detailed Design Implementation Production Transition Production Transition DO-254 Lifecycle Planning PHAC

DO-254 Principles Move to Higher Levels 6 End-Product (System) Requirements Customer Requirements Management & Tracing Chip Design & Analysis Board Design & Analysis System Design & Analysis DO-254

Managing the Design and Virtual Prototyping Process Enterprise Requirements Database Design IP Verification IP IP System Integration/Test Component Test Architecture Validation/Test Functional Verification Requirements Verification Requirements Definition Functional Design Architecture Design System Design Component Design AdvancedRequirementsTracingEngine

Overall Objective n Produce a traceable “Verified Implementation” — Requirements Coverage n Demonstrate that all the requirements have been implemented. — Functional Coverage n Demonstrate that the required design functionality has been fully tested — Change Tracking and Control n Track requirements changes and manage their impact throughout the development process.

Tracing Requirements into FPGA/ASIC Design n RTL Code — Associate HDL design constructs with design requirements n Verification Plan — Associate verification requirements with design requirements n Testbench Code — Associate HDL testbench constructs and coverage items with verification requirements n Verification Results — Associate verification results, such as text logs and coverage databases, with verification requirements. VHDL Verilog VHDL Verilog Log Files Log Files

The Challenge: Tracing Requirements down into the Implementation and Verification Details Wide variety of data to track: n System Level Requirements (DOORs) n Subsystem Specification (Word) n Design Source (VHDL) n Test Plan (Excel) n Testbench (SystemVerilog) n Simulation Verification Results (UCDB & text logs) n Hardware Test Results (Instrument &ATE logs)

Tracing Requirements into FPGA/ASIC Design

Tracing Requirements into PCB Design n Schematic — Associate a schematic block with a requirement n Constraints — Associate constraints on a net with a requirement n Layout — Associate an area of a layout with a requirement n Verification Results — Associate results from PCB verfication tools such as signal integrity, manufacturability and thermal analysis with a requirement Log Files Log Files

Tracing Requirements into PCB Design

Tracing Requirements into ESL Design n Functional Model — Associate requirements with a system level functional model n Architectural Model / Virtual Prototype — Associate requirements with an architectural level model n TLM Model — Associate requirements with a TLM model n Model Verification Results — Associate requirements with results from all levels of model simulations Log Files Log Files C / C++/ SysC UML / C / C++ TLM / SysC

Tracing Requirements into ESL Design

Tracing Requirements into EWIS Design n Design — Associate requirements with EWIS design elements n Constraints — Associate requirements with EWIS constraint definitions n FMEA Results — Associate requirements with results of Failure Modes and Effects analysis n EWIS Verification Results — Associate requirements with simulation results for DC, transient sneak path and switch state analysis Log Files Log Files CHS

Tracing Requirements into EWIS Design

ESL Flow EWIS Flow 18 FPGA Assurance Workshop, Feb 2009 Requirements Driven Development Process n Customer Level n System Level n Subsystem Level n Module/LRU Level n ASIC/FPGA Level PCB Flow ASIC/FPGA Flow

19 Requirements Volatility n Definition — A measure of the number of new, deleted and changed requirements relative to the total number of requirements n Impact — System Quality — Development Schedules n Measurement — Can be Difficult (An automated tool really helps!) — Powerful project management tool

20 C / C++ Design and Testbench Source Files & PCB Design Data ASCII Test Results Enterprise Level Requirements Databases Requirements Documents &Text Files Requirements Tracing with ReqTracer Change Impact and Traceability Analysis Automated Traceability Report Generation Requirements-aware Access to Test Result Data ReqTracer VHDL Verilog Text Log Files Text Log Files Matlab™ Simulation Results

Tag n Configure ReqTracer to capture existing requirements n Tag new requirements DesignSpecification REQ_001REQ_001 REQ_002REQ_002 REQ_004REQ_004 REQ_003REQ_003 REQ_005REQ_005 TAGTAG TAGTAG TAGTAG TAGTAG TAGTAG

DesignSpecificationRTLDesign IMPLEMENTS Trace HardwareRequirements COVERS COVERS COVERS IMPLEMENTS IMPLEMENTS IMPLEMENTS 40%40%60%60% Hardware Designers What shall I work on next? Certification Authority Can you prove all requirements are implemented and tested? System Architect What is this code for?

Can we make a change and still release on time? Project Manager DesignSpecificationRTLDesign IMPLEMENTS Monitor/Analyze HardwareRequirements COVERS COVERS COVERS IMPLEMENTS IMPLEMENTS IMPLEMENTS CHANGECHANGEIMPACTIMPACT IMPACTIMPACT IMPACTIMPACT IMPACTIMPACT 20% 40% 60%60% System Architect How risky would it be if I changed this? Quality Manager Which tests need updating now the design has changed? IMPACTIMPACT

Basic vs. Advanced Requirements Tracing n Basic — DOORS Support — Word/Excel Support — Design Artifact Import — External Filename Ref — Traceability Report — CM Mechanism n Advanced — DOORS Interface — Word/Excel Interface — Text File Interface — Design Data Interfaces — Data Environment Link — Design Tool Interfaces — Requirements Aware Change Tracking — Traceability Report — Report Library — Programmable Report Generator — IP-Safe Interactive Tracing Report

Advanced Requirements Tracing n Advanced — DOORS Interface — Word/Excel Interface — Test File Interface — Design Data Interfaces — Data Environment Link — Design Tool Interfaces — Requirements Aware Change Tracking — Traceability Report — Report Library — Programmable Report Generator — IP-Safe Interactive Tracing Report

Traceability Across Design Domains Enterprise Requirements Database Electrical DesignMechanical Design Software Design IP EE ME SW Advanced Requirements Tracing Engine WCR, IESF Seattle, May

Enterprise Requirements Database Advanced Requirements Tracing Engine Traceability across the Supply Chain In-House Supplier B Supplier A EE MEME SWSW ME SW EE ME SWSW IP WCR, IESF Seattle, May

28 ReqTracer ™ Managing Requirements throughout your Design Flows Analysis & Reporting Change Management Impact Analysis to Control Schedules Requirements Capture & Tracing XML ASCII Link Automated Reports, Specs, Design & Results Trace Through Deign Implementation & Testing

Presenter Initials, IESF Seattle, May