Ivanovici1 MAPLD 2005 / 152 Assessing Application Performance in Degraded Network Environments – An FPGA-based Approach – Mihai Ivanovici CERN, Geneva & POLITEHNICA University, Bucharest Dr. Razvan Beuran CERN, Geneva & POLITEHNICA University, Bucharest Dr. Neil Davies Predictable Network Solutions, Bristol

2MAPLD 2005 / 152 Ivanovici Outline Motivation  Application performance assessment methodology Network emulator architecture  Implementation considerations  The hardware platform Experimental results  Short-lived HTTP transfers over large delay connections Conclusions & future work Acknowledgements

3MAPLD 2005 / 152 Ivanovici Motivation Rationale: methodology for assessing the effects of network quality degradation on applications CERN’s interest  Long-distance networks have high costs  must make an optimal use of resources What affects applications is not so much “quality” as the “quality degradation” (ΔQ) experienced  This is something we can reproduce in the laboratory

4MAPLD 2005 / 152 Ivanovici Influence of quality degradation on application outcome Interaction of Quality Degradation (ΔQ) and User-Perceived Quality (UPQ) for VoIP (G.711) Applications only care about the outcome, not the mechanisms

5MAPLD 2005 / 152 Ivanovici Networks = Degraded Environments Assess application performance under varying network conditions

6MAPLD 2005 / 152 Ivanovici Assessing application performance Simultaneously  Measure the network quality degradation (ΔQ)  Assess the UPQ for the application under test

7MAPLD 2005 / 152 Ivanovici Reproducible & controllable conditions Network emulation  Hybrid technique that uses real applications  Wide range of network conditions

8MAPLD 2005 / 152 Ivanovici The architecture Replaceable modular components

9MAPLD 2005 / 152 Ivanovici Implementation philosophy Use of message passing  Abstraction  reusability & independent module design  Asynchronous concurrent processes (18) Use of Handel-C  The concept of channels (CSP, Occam)  Rapid development and translation into hardware  Easy debugging due to channel-based architecture Flexible (custom) design  Other projects: GE tester, sniffers, traffic emulators

10MAPLD 2005 / 152 Ivanovici The hardware platform 1 Altera Stratix FPGA (25 k LEs) 2 GE PHYs 128 MB SDRAM 2 MB SSRAM 1 FLASH memory 3V3 PCI connector IP cores:  MAC IP core  PCI controller  SDRAM controller

11MAPLD 2005 / 152 Ivanovici Architectural choice – SDRAM access Direct access / semaphoreClient / Server architecture Inter-domain data transfers using channels are slow (4 cycles per word) Inter-domain data transfers using dual-port on-chip RAM are fast (1 cycle/word) 8-word burst SDRAM operations >600 lines of code~300 lines of code Achieved rate: 400 Mb/sAchieved rate: 1 Gb/s

12MAPLD 2005 / 152 Ivanovici The SDRAM Server while( 1 ) prialt { casesdram_read_request_channel ? operation: par { sdr0_read_burst8(memory_address, context); sdr1_read_burst8(memory_address, context); } sdram_read_response_channel ! (unsigned 1) 1; break; casesdram_write_request_channel ? operation: par { sdr0_write_burst8(memory_address, context); sdr1_write_burst8(memory_address, context); } sdram_write_response_channel ! (unsigned 1) 1; break; } Channel selection Read 8-word bursts from SDRAM #0 & #1 Confirm operation completion Write 8-word bursts to SDRAM #0 & #1 Confirm operation completion

13MAPLD 2005 / 152 Ivanovici HTTP test results  Site download duration vs. offered background traffic load

14MAPLD 2005 / 152 Ivanovici Current emulators Do exist  Mainly software based Packet by packet systems  Independent loss and delay applied to packets  unrealistic behaviour  False packet reordering  Intra-stream contention not modeled

15MAPLD 2005 / 152 Ivanovici Why another emulator? More realistic scenarios  Intra-stream and inter-stream contention Correlated loss and delay, natural induced jitter  Phase / mode changes in network Topology or environment changes (e.g. wireless) More flexibility and control on the degradation models

16MAPLD 2005 / 152 Ivanovici Conclusions Methodology for assessing application performance Network emulator  Use FPGA  1 G/s bidirectional  High-accuracy operation  Realistic effects through the use of intra- and inter- stream contention mechanisms

17MAPLD 2005 / 152 Ivanovici Future work Emulate multiple hops Implement server with vacations algorithms Aggregate models of queues and wires into one single model Build a new board  Bigger and faster FPGA  External (USB connected)  Larger SDRAM

18MAPLD 2005 / 152 Ivanovici Acknowledgments Brian Martin and Jaroslav Pech for designing the board Matei Ciobotaru for implementing the low-level libraries for access to board components