ATLAS SCT/Pixel TIM FDR/PRR 28 July 2004 Interfaces to ROD Crate Components - Matt Warren1 Physics & Astronomy HEP Electronics Matthew Warren John Lane,

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Presentation transcript:

ATLAS SCT/Pixel TIM FDR/PRR 28 July 2004 Interfaces to ROD Crate Components - Matt Warren1 Physics & Astronomy HEP Electronics Matthew Warren John Lane, Martin Postranecky TIM Interfaces to ROD Crate Components ATLAS SCT TIM FDR/PRR 28 June 2004

ATLAS SCT/Pixel TIM FDR/PRR 28 July 2004 Interfaces to ROD Crate Components - Matt Warren2 Overview TIM located in center of ROD crate (slot 13) for optimal signal paths. Sends Clock and Control signals over a custom J3 backplane. Receives TTC Signals into front-panel via optical fibre. RCC ROD/ BOC 1-8 ROD/ BOC 9-16 ROD Crate TIM!

ATLAS SCT/Pixel TIM FDR/PRR 28 July 2004 Interfaces to ROD Crate Components - Matt Warren3 TIM Connections Overview BOC ROD (Rea d-Out Drive r) ROD FP/PO Resets ROD (Rea d-Out Drive r) ROD Signals Busses ROD (Rea d-Out Drive r) Front-End Modules Clock & Control (optical) (48/BOC) ROD Busys MRMW v Clocks Fanout TTC (optical) ROD Crate Busy VME NIM / ECL Signals ROD Read-Out Driver RCC ROD Crate Controller BOC Back Of Crate TIM TTC Interface Module TIM-OK

ATLAS SCT/Pixel TIM FDR/PRR 28 July 2004 Interfaces to ROD Crate Components - Matt Warren4 ROD-Crate-Controller Interface Standard VME Slave A24/A32 D16 D32 (top word unused) Preset or Geographical base-address TIM TTC Interface Module RCC ROD Crate Controller

ATLAS SCT/Pixel TIM FDR/PRR 28 July 2004 Interfaces to ROD Crate Components - Matt Warren5 Back-Of-Crate Interface TIM distributes the BC clock to the BOC –BOC feeds clock to ROD in same slot To minimise Skew/Jitter: –point-to-point same length lines –differential signalling (PECL) BOC TIM BOC Back Of Crate

ATLAS SCT/Pixel TIM FDR/PRR 28 July 2004 Interfaces to ROD Crate Components - Matt Warren6 Read-Out Driver Interface ROD (Rea d-Out Drive r) ROD FP/PO Resets ROD (Rea d-Out Drive r) ROD ROD (Rea d-Out Drive r) ROD TIM TIM distributes 8 Control Signals to RODs As TIM is in the middle of crate, there are 2 busses - left and right - terminated at ends. TIM is can adjust phase of the signals to satisfy ROD’s setup and hold times. Signal assignment is flexible –can be re-mapped in firmware Signals active for one clock period. TIM introduces dead-time after its stand-alone signals to compensate for longer FE signals from the ROD.

ATLAS SCT/Pixel TIM FDR/PRR 28 July 2004 Interfaces to ROD Crate Components - Matt Warren7 Control Signals Description L1A – Level-1 Trigger Accept ECR – Reset Event Counter (L1ID) First L1A after ECR is zero BCR – Reset Bunch Counter (BCID)- once per LHC orbit BCID value is in the range 0 – 3563 with LHC orbit BCRs. If no BCR occurs, BCID is 0 – CAL – Calibration pulse command for front-end amplifiers SID – Serialised Trigger ID - 24 L1ID + 12 BCID bits STT – Serialised Trigger Type - 8 TType + 2 reserved bits ID's have a single start bit, no stop bit SID, STT values are independently queued before TX FER – Reserved - could be a separate periodic reset signal SPR –Spare

ATLAS SCT/Pixel TIM FDR/PRR 28 July 2004 Interfaces to ROD Crate Components - Matt Warren8 ROD Busy/TIM-OK ROD (Rea d-Out Drive r) ROD FP/PO Resets ROD (Rea d-Out Drive r) ROD ROD (Rea d-Out Drive r) ROD Read-Out Driver TIM ROD-Busy Received by TIM from RODs. point-to-point signal. Active low, pulled high on TIM –So empty slots are not indicated busy. TIM-OK Bussed to all slots in crate. Pulled down. Asserted when selected TIM clock is good.